211 static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)  in ethoc_write()  function
228 	ethoc_write(priv, offset + 0, bd->stat);  in ethoc_write_bd()
229 	ethoc_write(priv, offset + 4, bd->addr);  in ethoc_write_bd()
234 	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |  in ethoc_write_hwaddr_common()
236 	ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));  in ethoc_write_hwaddr_common()
242 	ethoc_write(priv, INT_SOURCE, mask);  in ethoc_ack_irq()
249 	ethoc_write(priv, MODER, mode);  in ethoc_enable_rx_and_tx()
256 	ethoc_write(priv, MODER, mode);  in ethoc_disable_rx_and_tx()
317 	ethoc_write(priv, MODER, mode);  in ethoc_reset()
322 	ethoc_write(priv, MODER, mode);  in ethoc_reset()
323 	ethoc_write(priv, IPGT, 0x15);  in ethoc_reset()
336 	ethoc_write(priv, TX_BD_NUM, priv->num_tx);  in ethoc_init_common()
547 	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));  in ethoc_mdio_read()
548 	ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);  in ethoc_mdio_read()
557 		ethoc_write(priv, MIICOMMAND, 0);  in ethoc_mdio_read()
569 	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));  in ethoc_mdio_write()
570 	ethoc_write(priv, MIITX_DATA, val);  in ethoc_mdio_write()
571 	ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);  in ethoc_mdio_write()
578 		ethoc_write(priv, MIICOMMAND, 0);  in ethoc_mdio_write()