Lines Matching refs:port
81 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
82 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
87 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
108 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
109 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
110 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
111 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
112 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
113 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
114 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
115 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
128 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) argument
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) argument
141 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) argument
143 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) argument
248 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) argument
251 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) argument
260 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) argument
349 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) argument
497 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \ argument
498 (0x4 * (port)))
887 #define MVPP2_BM_SWF_LONG_POOL(port) 0 argument
1188 int port; member
1307 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_set() argument
1311 if (port->priv->hw_version == MVPP21) { in mvpp2_txdesc_dma_addr_set()
1321 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, in mvpp2_txdesc_size_set() argument
1325 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_set()
1331 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, in mvpp2_txdesc_txq_set() argument
1335 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_txq_set()
1341 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, in mvpp2_txdesc_cmd_set() argument
1345 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_cmd_set()
1351 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, in mvpp2_txdesc_offset_set() argument
1355 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_offset_set()
1361 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_rxdesc_dma_addr_get() argument
1364 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_dma_addr_get()
1370 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, in mvpp2_rxdesc_cookie_get() argument
1373 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_cookie_get()
1379 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, in mvpp2_rxdesc_size_get() argument
1382 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_size_get()
1388 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, in mvpp2_rxdesc_status_get() argument
1391 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_status_get()
1405 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
1407 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
1411 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
1413 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
1504 unsigned int port, bool add) in mvpp2_prs_tcam_port_set() argument
1509 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1511 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1772 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_drop_all_set() argument
1801 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1807 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_promisc_set() argument
1842 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1848 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, in mvpp2_prs_mac_multi_set() argument
1891 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1897 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, in mvpp2_prs_hw_port_init() argument
1904 val &= ~MVPP2_PRS_PORT_LU_MASK(port); in mvpp2_prs_hw_port_init()
1905 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); in mvpp2_prs_hw_port_init()
1909 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); in mvpp2_prs_hw_port_init()
1910 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); in mvpp2_prs_hw_port_init()
1911 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); in mvpp2_prs_hw_port_init()
1912 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
1917 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); in mvpp2_prs_hw_port_init()
1918 val &= ~MVPP2_PRS_INIT_OFF_MASK(port); in mvpp2_prs_hw_port_init()
1919 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); in mvpp2_prs_hw_port_init()
1920 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); in mvpp2_prs_hw_port_init()
1927 int port; in mvpp2_prs_def_flow_init() local
1929 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_prs_def_flow_init()
1932 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1938 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
2325 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, in mvpp2_prs_mac_da_accept() argument
2334 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
2369 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
2414 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da) in mvpp2_prs_update_mac_da() argument
2419 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr, in mvpp2_prs_update_mac_da()
2425 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); in mvpp2_prs_update_mac_da()
2430 memcpy(port->dev_addr, da, ETH_ALEN); in mvpp2_prs_update_mac_da()
2436 static int mvpp2_prs_def_flow(struct mvpp2_port *port) in mvpp2_prs_def_flow() argument
2441 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
2446 tid = mvpp2_prs_tcam_first_free(port->priv, in mvpp2_prs_def_flow()
2460 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2464 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2467 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
2468 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
2526 static void mvpp2_cls_port_config(struct mvpp2_port *port) in mvpp2_cls_port_config() argument
2532 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); in mvpp2_cls_port_config()
2533 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); in mvpp2_cls_port_config()
2534 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); in mvpp2_cls_port_config()
2539 le.lkpid = port->id; in mvpp2_cls_port_config()
2545 le.data |= port->first_rxq; in mvpp2_cls_port_config()
2551 mvpp2_cls_lookup_write(port->priv, &le); in mvpp2_cls_port_config()
2555 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) in mvpp2_cls_oversize_rxq_set() argument
2559 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2560 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); in mvpp2_cls_oversize_rxq_set()
2562 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2563 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); in mvpp2_cls_oversize_rxq_set()
2565 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set()
2566 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); in mvpp2_cls_oversize_rxq_set()
2567 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
2713 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
2720 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
2722 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_long_pool_set()
2727 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
2730 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
2751 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
2755 if (port->priv->hw_version == MVPP22) { in mvpp2_bm_pool_put()
2767 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val); in mvpp2_bm_pool_put()
2775 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); in mvpp2_bm_pool_put()
2776 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); in mvpp2_bm_pool_put()
2780 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, in mvpp2_pool_refill() argument
2786 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_pool_refill()
2790 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
2797 netdev_err(port->dev, in mvpp2_bm_bufs_add()
2804 mvpp2_bm_pool_put(port, bm_pool->id, in mvpp2_bm_bufs_add()
2820 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, in mvpp2_bm_pool_use() argument
2823 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
2827 netdev_err(port->dev, "mixing pool types is forbidden\n"); in mvpp2_bm_pool_use()
2851 port->priv, new_pool); in mvpp2_bm_pool_use()
2856 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
2868 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
2872 if (!port->pool_long) { in mvpp2_swf_bm_pool_init()
2873 port->pool_long = in mvpp2_swf_bm_pool_init()
2874 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), in mvpp2_swf_bm_pool_init()
2876 port->pkt_size); in mvpp2_swf_bm_pool_init()
2877 if (!port->pool_long) in mvpp2_swf_bm_pool_init()
2880 port->pool_long->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
2883 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init()
2891 static void mvpp2_port_mii_set(struct mvpp2_port *port) in mvpp2_port_mii_set() argument
2895 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2897 switch (port->phy_interface) { in mvpp2_port_mii_set()
2908 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2911 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) in mvpp2_port_fc_adv_enable() argument
2915 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2917 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2920 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
2924 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2927 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2930 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
2934 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2936 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2940 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
2944 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
2946 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
2950 static void mvpp2_port_loopback_set(struct mvpp2_port *port) in mvpp2_port_loopback_set() argument
2954 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2956 if (port->speed == 1000) in mvpp2_port_loopback_set()
2961 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_port_loopback_set()
2966 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2969 static void mvpp2_port_reset(struct mvpp2_port *port) in mvpp2_port_reset() argument
2973 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2975 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_reset()
2977 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2983 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
2987 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2989 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
2991 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2997 static int gop_gmac_reset(struct mvpp2_port *port, int reset) in gop_gmac_reset() argument
3002 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
3007 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
3017 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en) in gop_gpcs_mode_cfg() argument
3021 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
3027 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
3032 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) in gop_bypass_clk_cfg() argument
3036 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3042 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3047 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) in gop_gmac_sgmii2_5_cfg() argument
3056 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3059 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3062 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3068 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3070 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3076 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3086 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii2_5_cfg()
3089 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) in gop_gmac_sgmii_cfg() argument
3098 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3101 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3104 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3110 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3112 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3115 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3124 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii_cfg()
3127 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port) in gop_gmac_rgmii_cfg() argument
3136 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3139 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3142 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3148 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3150 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3153 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3161 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_rgmii_cfg()
3165 static int gop_gmac_mode_cfg(struct mvpp2_port *port) in gop_gmac_mode_cfg() argument
3170 switch (port->phy_interface) { in gop_gmac_mode_cfg()
3172 if (port->phy_speed == 2500) in gop_gmac_mode_cfg()
3173 gop_gmac_sgmii2_5_cfg(port); in gop_gmac_mode_cfg()
3175 gop_gmac_sgmii_cfg(port); in gop_gmac_mode_cfg()
3180 gop_gmac_rgmii_cfg(port); in gop_gmac_mode_cfg()
3188 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3191 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3194 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3196 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3201 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port) in gop_xlg_2_gig_mac_cfg() argument
3206 if (port->gop_id > 0) in gop_xlg_2_gig_mac_cfg()
3210 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3213 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3216 static int gop_gpcs_reset(struct mvpp2_port *port, int reset) in gop_gpcs_reset() argument
3220 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3225 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3231 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes) in gop_xpcs_mode() argument
3251 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3255 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3260 static int gop_mpcs_mode(struct mvpp2_port *port) in gop_mpcs_mode() argument
3265 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3267 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3270 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3273 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3279 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3285 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes) in gop_xlg_mac_mode_cfg() argument
3290 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3292 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3294 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3297 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3300 val = readl(port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3305 writel(val, port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3308 val = readl(port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3311 writel(val, port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3314 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3317 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3323 static int gop_xpcs_reset(struct mvpp2_port *port, int reset) in gop_xpcs_reset() argument
3328 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3333 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3339 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset) in gop_xlg_mac_reset() argument
3344 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3349 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3362 static int gop_port_init(struct mvpp2_port *port) in gop_port_init() argument
3364 int mac_num = port->gop_id; in gop_port_init()
3373 switch (port->phy_interface) { in gop_port_init()
3376 gop_gmac_reset(port, 1); in gop_port_init()
3379 gop_gpcs_mode_cfg(port, 0); in gop_port_init()
3380 gop_bypass_clk_cfg(port, 1); in gop_port_init()
3383 gop_gmac_mode_cfg(port); in gop_port_init()
3385 gop_gpcs_reset(port, 0); in gop_port_init()
3388 gop_gmac_reset(port, 0); in gop_port_init()
3393 gop_gpcs_mode_cfg(port, 1); in gop_port_init()
3396 gop_gmac_mode_cfg(port); in gop_port_init()
3398 gop_xlg_2_gig_mac_cfg(port); in gop_port_init()
3401 gop_gpcs_reset(port, 0); in gop_port_init()
3403 gop_gmac_reset(port, 0); in gop_port_init()
3410 gop_xpcs_mode(port, num_of_act_lanes); in gop_port_init()
3411 gop_mpcs_mode(port); in gop_port_init()
3413 gop_xlg_mac_mode_cfg(port, num_of_act_lanes); in gop_port_init()
3416 gop_xpcs_reset(port, 0); in gop_port_init()
3419 gop_xlg_mac_reset(port, 0); in gop_port_init()
3424 __func__, port->phy_interface); in gop_port_init()
3431 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable) in gop_xlg_mac_port_enable() argument
3435 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3444 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3447 static void gop_port_enable(struct mvpp2_port *port, int enable) in gop_port_enable() argument
3449 switch (port->phy_interface) { in gop_port_enable()
3454 mvpp2_port_enable(port); in gop_port_enable()
3456 mvpp2_port_disable(port); in gop_port_enable()
3460 gop_xlg_mac_port_enable(port, enable); in gop_port_enable()
3465 port->phy_interface); in gop_port_enable()
3708 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
3712 if (port->priv->hw_version == MVPP21) { in mvpp2_defaults_set()
3714 if (port->flags & MVPP2_F_LOOPBACK) in mvpp2_defaults_set()
3715 mvpp2_port_loopback_set(port); in mvpp2_defaults_set()
3718 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3722 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3726 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
3727 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
3729 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
3733 ptxq = mvpp2_txq_phys(port->id, queue); in mvpp2_defaults_set()
3734 mvpp2_write(port->priv, in mvpp2_defaults_set()
3741 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8); in mvpp2_defaults_set()
3742 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
3746 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
3748 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
3751 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
3757 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
3758 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
3761 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3766 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
3772 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
3773 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
3775 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
3779 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
3785 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
3786 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
3788 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
3795 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
3799 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
3804 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
3810 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
3811 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
3817 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
3821 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
3824 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
3825 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
3828 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
3835 netdev_warn(port->dev, in mvpp2_egress_disable()
3846 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
3854 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
3856 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
3865 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
3873 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
3888 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
3896 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
3903 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
3907 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port, in mvpp2_bm_cookie_build() argument
3913 pool = (mvpp2_rxdesc_status_get(port, rx_desc) & in mvpp2_bm_cookie_build()
3924 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port, in mvpp2_txq_pend_desc_num_get() argument
3929 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_pend_desc_num_get()
3930 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_pend_desc_num_get()
3946 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
3949 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); in mvpp2_aggr_txq_pend_desc_add()
3956 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
3962 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id)); in mvpp2_txq_sent_desc_proc()
3970 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
3974 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
3976 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id)); in mvpp2_txq_sent_counter_clear()
3981 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
3986 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
3994 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
3995 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
3998 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
4001 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
4004 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
4010 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
4014 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
4022 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
4030 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
4040 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
4045 return port->rxqs[queue]; in mvpp2_get_rx_queue()
4048 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
4053 return port->txqs[queue]; in mvpp2_get_tx_queue()
4098 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
4104 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
4118 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
4121 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
4122 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_init()
4126 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
4127 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
4128 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
4131 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); in mvpp2_rxq_init()
4134 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
4140 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
4145 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
4151 u32 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_rxq_drop_pkts()
4153 mvpp2_pool_refill(port, bm, in mvpp2_rxq_drop_pkts()
4154 mvpp2_rxdesc_dma_addr_get(port, rx_desc), in mvpp2_rxq_drop_pkts()
4155 mvpp2_rxdesc_cookie_get(port, rx_desc)); in mvpp2_rxq_drop_pkts()
4157 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
4161 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
4164 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
4174 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
4175 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
4176 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
4177 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
4181 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
4188 txq->size = port->tx_ring_size; in mvpp2_txq_init()
4203 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
4204 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma); in mvpp2_txq_init()
4205 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & in mvpp2_txq_init()
4207 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
4208 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
4210 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
4212 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
4220 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
4223 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
4228 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
4229 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
4231 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
4235 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
4238 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
4250 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
4259 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); in mvpp2_txq_deinit()
4262 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
4263 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
4264 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
4268 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
4274 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
4275 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
4277 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4285 netdev_warn(port->dev, in mvpp2_txq_clean()
4287 port->id, txq->log_id); in mvpp2_txq_clean()
4293 pending = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_txq_clean()
4297 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4303 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
4313 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
4319 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
4322 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4323 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4326 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
4327 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
4328 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
4331 mvpp2_txq_sent_counter_clear(port); in mvpp2_cleanup_txqs()
4333 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4334 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4338 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
4343 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
4347 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
4352 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
4359 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
4364 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
4370 txq = port->txqs[queue]; in mvpp2_setup_txqs()
4371 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
4376 mvpp2_txq_sent_counter_clear(port); in mvpp2_setup_txqs()
4380 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
4385 static void mvpp2_link_event(struct mvpp2_port *port) in mvpp2_link_event() argument
4387 struct phy_device *phydev = port->phy_dev; in mvpp2_link_event()
4392 if ((port->speed != phydev->speed) || in mvpp2_link_event()
4393 (port->duplex != phydev->duplex)) { in mvpp2_link_event()
4396 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4411 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4413 port->duplex = phydev->duplex; in mvpp2_link_event()
4414 port->speed = phydev->speed; in mvpp2_link_event()
4418 if (phydev->link != port->link) { in mvpp2_link_event()
4420 port->duplex = -1; in mvpp2_link_event()
4421 port->speed = 0; in mvpp2_link_event()
4424 port->link = phydev->link; in mvpp2_link_event()
4430 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4433 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4434 mvpp2_egress_enable(port); in mvpp2_link_event()
4435 mvpp2_ingress_enable(port); in mvpp2_link_event()
4437 mvpp2_ingress_disable(port); in mvpp2_link_event()
4438 mvpp2_egress_disable(port); in mvpp2_link_event()
4446 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
4449 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx_error()
4450 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx_error()
4454 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", in mvpp2_rx_error()
4458 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", in mvpp2_rx_error()
4462 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", in mvpp2_rx_error()
4469 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
4473 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr); in mvpp2_rx_refill()
4478 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
4480 switch (port->phy_interface) { in mvpp2_start_dev()
4484 mvpp2_gmac_max_rx_size_set(port); in mvpp2_start_dev()
4489 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
4491 if (port->priv->hw_version == MVPP21) in mvpp2_start_dev()
4492 mvpp2_port_enable(port); in mvpp2_start_dev()
4494 gop_port_enable(port, 1); in mvpp2_start_dev()
4498 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
4501 mvpp2_ingress_disable(port); in mvpp2_stop_dev()
4503 mvpp2_egress_disable(port); in mvpp2_stop_dev()
4505 if (port->priv->hw_version == MVPP21) in mvpp2_stop_dev()
4506 mvpp2_port_disable(port); in mvpp2_stop_dev()
4508 gop_port_enable(port, 0); in mvpp2_stop_dev()
4511 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) in mvpp2_phy_connect() argument
4515 if (!port->init || port->link == 0) { in mvpp2_phy_connect()
4516 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev, in mvpp2_phy_connect()
4517 port->phy_interface); in mvpp2_phy_connect()
4518 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4520 netdev_err(port->dev, "cannot connect to phy\n"); in mvpp2_phy_connect()
4526 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4527 port->link = 0; in mvpp2_phy_connect()
4528 port->duplex = 0; in mvpp2_phy_connect()
4529 port->speed = 0; in mvpp2_phy_connect()
4538 port->init = 1; in mvpp2_phy_connect()
4540 mvpp2_egress_enable(port); in mvpp2_phy_connect()
4541 mvpp2_ingress_enable(port); in mvpp2_phy_connect()
4547 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port) in mvpp2_open() argument
4553 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); in mvpp2_open()
4558 err = mvpp2_prs_mac_da_accept(port->priv, port->id, in mvpp2_open()
4559 port->dev_addr, true); in mvpp2_open()
4564 err = mvpp2_prs_def_flow(port); in mvpp2_open()
4571 err = mvpp2_setup_rxqs(port); in mvpp2_open()
4573 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
4577 err = mvpp2_setup_txqs(port); in mvpp2_open()
4579 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
4583 if (port->phy_node) { in mvpp2_open()
4584 err = mvpp2_phy_connect(dev, port); in mvpp2_open()
4588 mvpp2_link_event(port); in mvpp2_open()
4590 mvpp2_egress_enable(port); in mvpp2_open()
4591 mvpp2_ingress_enable(port); in mvpp2_open()
4594 mvpp2_start_dev(port); in mvpp2_open()
4603 static void mvpp2_port_power_up(struct mvpp2_port *port) in mvpp2_port_power_up() argument
4605 struct mvpp2 *priv = port->priv; in mvpp2_port_power_up()
4609 mvpp2_port_mii_set(port); in mvpp2_port_power_up()
4610 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_power_up()
4612 mvpp2_port_fc_adv_enable(port); in mvpp2_port_power_up()
4613 mvpp2_port_reset(port); in mvpp2_port_power_up()
4617 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) in mvpp2_port_init() argument
4619 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
4623 if (port->first_rxq + rxq_number > in mvpp2_port_init()
4628 mvpp2_egress_disable(port); in mvpp2_port_init()
4630 mvpp2_port_disable(port); in mvpp2_port_init()
4632 gop_port_enable(port, 0); in mvpp2_port_init()
4634 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), in mvpp2_port_init()
4636 if (!port->txqs) in mvpp2_port_init()
4643 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
4663 port->txqs[queue] = txq; in mvpp2_port_init()
4666 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs), in mvpp2_port_init()
4668 if (!port->rxqs) in mvpp2_port_init()
4680 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
4681 rxq->port = port->id; in mvpp2_port_init()
4684 port->rxqs[queue] = rxq; in mvpp2_port_init()
4690 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
4692 rxq->size = port->rx_ring_size; in mvpp2_port_init()
4697 mvpp2_ingress_disable(port); in mvpp2_port_init()
4700 mvpp2_defaults_set(port); in mvpp2_port_init()
4703 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
4704 mvpp2_cls_port_config(port); in mvpp2_port_init()
4707 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN); in mvpp2_port_init()
4710 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
4717 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) in phy_info_parse() argument
4751 port->priv->mdio_base = (void *)mdio_addr; in phy_info_parse()
4753 if (port->priv->mdio_base < 0) { in phy_info_parse()
4777 &port->phy_reset_gpio, GPIOD_IS_OUT); in phy_info_parse()
4779 &port->phy_tx_disable_gpio, GPIOD_IS_OUT); in phy_info_parse()
4788 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node, in phy_info_parse()
4791 port->id = id; in phy_info_parse()
4792 if (port->priv->hw_version == MVPP21) in phy_info_parse()
4793 port->first_rxq = port->id * rxq_number; in phy_info_parse()
4795 port->first_rxq = port->id * port->priv->max_port_rxqs; in phy_info_parse()
4796 port->phy_node = phy_node; in phy_info_parse()
4797 port->phy_interface = phy_mode; in phy_info_parse()
4798 port->phyaddr = phyaddr; in phy_info_parse()
4805 static void mvpp2_gpio_init(struct mvpp2_port *port) in mvpp2_gpio_init() argument
4807 if (dm_gpio_is_valid(&port->phy_reset_gpio)) { in mvpp2_gpio_init()
4808 dm_gpio_set_value(&port->phy_reset_gpio, 0); in mvpp2_gpio_init()
4810 dm_gpio_set_value(&port->phy_reset_gpio, 1); in mvpp2_gpio_init()
4813 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio)) in mvpp2_gpio_init()
4814 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0); in mvpp2_gpio_init()
4820 struct mvpp2_port *port, in mvpp2_port_probe() argument
4826 port->tx_ring_size = MVPP2_MAX_TXD; in mvpp2_port_probe()
4827 port->rx_ring_size = MVPP2_MAX_RXD; in mvpp2_port_probe()
4829 err = mvpp2_port_init(dev, port); in mvpp2_port_probe()
4831 dev_err(&pdev->dev, "failed to init port %d\n", port->id); in mvpp2_port_probe()
4834 mvpp2_port_power_up(port); in mvpp2_port_probe()
4837 mvpp2_gpio_init(port); in mvpp2_port_probe()
4840 priv->port_list[port->id] = port; in mvpp2_port_probe()
4881 int port; in mvpp2_rx_fifo_init() local
4883 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
4885 if (port == 0) { in mvpp2_rx_fifo_init()
4887 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4890 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4892 } else if (port == 1) { in mvpp2_rx_fifo_init()
4894 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4897 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4901 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4904 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4908 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4910 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4923 int port, val; in mvpp2_tx_fifo_init() local
4925 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_tx_fifo_init()
4927 if (port == 0) { in mvpp2_tx_fifo_init()
4934 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
5187 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_recv() local
5198 rxq = port->rxqs[0]; in mvpp2_recv()
5201 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_recv()
5208 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_recv()
5209 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_recv()
5211 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_recv()
5213 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_recv()
5215 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_recv()
5223 mvpp2_rx_error(port, rx_desc); in mvpp2_recv()
5225 mvpp2_pool_refill(port, bm, dma_addr, dma_addr); in mvpp2_recv()
5229 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr); in mvpp2_recv()
5231 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_recv()
5237 mvpp2_rxq_status_update(port, rxq->id, 1, 1); in mvpp2_recv()
5256 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_send() local
5262 txq = port->txqs[0]; in mvpp2_send()
5263 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; in mvpp2_send()
5267 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_send()
5268 mvpp2_txdesc_size_set(port, tx_desc, length); in mvpp2_send()
5269 mvpp2_txdesc_offset_set(port, tx_desc, in mvpp2_send()
5271 mvpp2_txdesc_dma_addr_set(port, tx_desc, in mvpp2_send()
5274 mvpp2_txdesc_cmd_set(port, tx_desc, in mvpp2_send()
5284 mvpp2_aggr_txq_pend_desc_add(port, 1); in mvpp2_send()
5286 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_send()
5294 tx_done = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_send()
5303 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_send()
5312 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_start() local
5315 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN); in mvpp2_start()
5318 mvpp2_prs_update_mac_da(port, port->dev_addr); in mvpp2_start()
5320 switch (port->phy_interface) { in mvpp2_start()
5324 mvpp2_port_power_up(port); in mvpp2_start()
5329 mvpp2_open(dev, port); in mvpp2_start()
5336 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_stop() local
5338 mvpp2_stop_dev(port); in mvpp2_stop()
5339 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
5340 mvpp2_cleanup_txqs(port); in mvpp2_stop()
5343 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) in mvpp22_smi_phy_addr_cfg() argument
5345 writel(port->phyaddr, port->priv->iface_base + in mvpp22_smi_phy_addr_cfg()
5346 MVPP22_SMI_PHY_ADDR_REG(port->gop_id)); in mvpp22_smi_phy_addr_cfg()
5451 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_probe() local
5459 port->priv = dev_get_priv(dev->parent); in mvpp2_probe()
5461 err = phy_info_parse(dev, port); in mvpp2_probe()
5472 port->base = (void __iomem *)devfdt_get_addr_index( in mvpp2_probe()
5473 dev->parent, priv_common_regs_num + port->id); in mvpp2_probe()
5474 if (IS_ERR(port->base)) in mvpp2_probe()
5475 return PTR_ERR(port->base); in mvpp2_probe()
5477 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in mvpp2_probe()
5479 if (port->id == -1) { in mvpp2_probe()
5484 port->base = priv->iface_base + MVPP22_PORT_BASE + in mvpp2_probe()
5485 port->gop_id * MVPP22_PORT_OFFSET; in mvpp2_probe()
5488 if(port->phy_node) in mvpp2_probe()
5489 mvpp22_smi_phy_addr_cfg(port); in mvpp2_probe()
5492 gop_port_init(port); in mvpp2_probe()
5506 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); in mvpp2_probe()
5511 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id, in mvpp2_probe()
5512 port->phy_interface); in mvpp2_probe()
5527 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_remove() local
5528 struct mvpp2 *priv = port->priv; in mvpp2_remove()