Lines Matching refs:phydev
106 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, in m88e1xxx_phy_extread() argument
109 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
112 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extread()
113 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
114 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extread()
119 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr, in m88e1xxx_phy_extwrite() argument
122 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
124 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extwrite()
125 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in m88e1xxx_phy_extwrite()
126 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extwrite()
132 static int m88e1011s_config(struct phy_device *phydev) in m88e1011s_config() argument
135 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
141 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1011s_config()
143 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
145 genphy_config_aneg(phydev); in m88e1011s_config()
153 static int m88e1xxx_parse_status(struct phy_device *phydev) in m88e1xxx_parse_status() argument
158 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
169 phydev->link = 0; in m88e1xxx_parse_status()
176 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
183 phydev->link = 1; in m88e1xxx_parse_status()
185 phydev->link = 0; in m88e1xxx_parse_status()
189 phydev->duplex = DUPLEX_FULL; in m88e1xxx_parse_status()
191 phydev->duplex = DUPLEX_HALF; in m88e1xxx_parse_status()
197 phydev->speed = SPEED_1000; in m88e1xxx_parse_status()
200 phydev->speed = SPEED_100; in m88e1xxx_parse_status()
203 phydev->speed = SPEED_10; in m88e1xxx_parse_status()
210 static int m88e1011s_startup(struct phy_device *phydev) in m88e1011s_startup() argument
214 ret = genphy_update_link(phydev); in m88e1011s_startup()
218 return m88e1xxx_parse_status(phydev); in m88e1011s_startup()
222 static int m88e1111s_config(struct phy_device *phydev) in m88e1111s_config() argument
226 if (phy_interface_is_rgmii(phydev)) { in m88e1111s_config()
227 reg = phy_read(phydev, in m88e1111s_config()
229 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || in m88e1111s_config()
230 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { in m88e1111s_config()
232 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in m88e1111s_config()
235 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in m88e1111s_config()
240 phy_write(phydev, in m88e1111s_config()
243 reg = phy_read(phydev, in m88e1111s_config()
253 phy_write(phydev, in m88e1111s_config()
257 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e1111s_config()
258 reg = phy_read(phydev, in m88e1111s_config()
265 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
269 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { in m88e1111s_config()
270 reg = phy_read(phydev, in m88e1111s_config()
273 phy_write(phydev, in m88e1111s_config()
276 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
281 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
285 phy_reset(phydev); in m88e1111s_config()
287 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
293 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
298 phy_reset(phydev); in m88e1111s_config()
300 genphy_config_aneg(phydev); in m88e1111s_config()
301 genphy_restart_aneg(phydev); in m88e1111s_config()
309 void m88e1518_phy_writebits(struct phy_device *phydev, in m88e1518_phy_writebits() argument
319 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); in m88e1518_phy_writebits()
324 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); in m88e1518_phy_writebits()
327 static int m88e1518_config(struct phy_device *phydev) in m88e1518_config() argument
337 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); in m88e1518_config()
338 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); in m88e1518_config()
339 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); in m88e1518_config()
340 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); in m88e1518_config()
341 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); in m88e1518_config()
342 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); in m88e1518_config()
343 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); in m88e1518_config()
344 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); in m88e1518_config()
345 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); in m88e1518_config()
346 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1518_config()
349 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e1518_config()
351 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18); in m88e1518_config()
354 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, in m88e1518_config()
358 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, in m88e1518_config()
362 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); in m88e1518_config()
367 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e1518_config()
368 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1518_config()
375 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1518_config()
379 if (phy_interface_is_rgmii(phydev)) { in m88e1518_config()
380 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); in m88e1518_config()
382 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); in m88e1518_config()
384 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in m88e1518_config()
385 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in m88e1518_config()
387 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in m88e1518_config()
389 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in m88e1518_config()
391 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); in m88e1518_config()
393 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); in m88e1518_config()
397 phy_reset(phydev); in m88e1518_config()
399 genphy_config_aneg(phydev); in m88e1518_config()
400 genphy_restart_aneg(phydev); in m88e1518_config()
406 static int m88e1510_config(struct phy_device *phydev) in m88e1510_config() argument
409 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, in m88e1510_config()
413 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL, in m88e1510_config()
418 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, in m88e1510_config()
422 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, in m88e1510_config()
427 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); in m88e1510_config()
429 return m88e1518_config(phydev); in m88e1510_config()
433 static int m88e1118_config(struct phy_device *phydev) in m88e1118_config() argument
436 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); in m88e1118_config()
438 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); in m88e1118_config()
440 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); in m88e1118_config()
442 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); in m88e1118_config()
444 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1118_config()
446 return genphy_config_aneg(phydev); in m88e1118_config()
449 static int m88e1118_startup(struct phy_device *phydev) in m88e1118_startup() argument
454 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1118_startup()
456 ret = genphy_update_link(phydev); in m88e1118_startup()
460 return m88e1xxx_parse_status(phydev); in m88e1118_startup()
464 static int m88e1121_config(struct phy_device *phydev) in m88e1121_config() argument
469 genphy_config_aneg(phydev); in m88e1121_config()
472 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); in m88e1121_config()
473 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, in m88e1121_config()
476 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, in m88e1121_config()
479 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); in m88e1121_config()
482 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); in m88e1121_config()
483 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); in m88e1121_config()
489 static int m88e1145_config(struct phy_device *phydev) in m88e1145_config() argument
494 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); in m88e1145_config()
495 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); in m88e1145_config()
496 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); in m88e1145_config()
497 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); in m88e1145_config()
499 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, in m88e1145_config()
502 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); in m88e1145_config()
503 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in m88e1145_config()
506 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); in m88e1145_config()
508 genphy_config_aneg(phydev); in m88e1145_config()
511 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1145_config()
513 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1145_config()
518 static int m88e1145_startup(struct phy_device *phydev) in m88e1145_startup() argument
522 ret = genphy_update_link(phydev); in m88e1145_startup()
526 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, in m88e1145_startup()
528 return m88e1xxx_parse_status(phydev); in m88e1145_startup()
532 static int m88e1149_config(struct phy_device *phydev) in m88e1149_config() argument
534 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); in m88e1149_config()
535 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1149_config()
536 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); in m88e1149_config()
537 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); in m88e1149_config()
538 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1149_config()
540 genphy_config_aneg(phydev); in m88e1149_config()
542 phy_reset(phydev); in m88e1149_config()
548 static int m88e1310_config(struct phy_device *phydev) in m88e1310_config() argument
553 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); in m88e1310_config()
554 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); in m88e1310_config()
556 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); in m88e1310_config()
559 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); in m88e1310_config()
560 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); in m88e1310_config()
562 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); in m88e1310_config()
565 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); in m88e1310_config()
566 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); in m88e1310_config()
568 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); in m88e1310_config()
571 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); in m88e1310_config()
573 return genphy_config_aneg(phydev); in m88e1310_config()
576 static int m88e1680_config(struct phy_device *phydev) in m88e1680_config() argument
586 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004); in m88e1680_config()
587 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27); in m88e1680_config()
589 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg); in m88e1680_config()
592 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd); in m88e1680_config()
593 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53); in m88e1680_config()
594 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d); in m88e1680_config()
595 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1680_config()
598 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); in m88e1680_config()
599 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030); in m88e1680_config()
600 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c); in m88e1680_config()
601 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc); in m88e1680_config()
602 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c); in m88e1680_config()
603 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c); in m88e1680_config()
604 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1680_config()
605 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in m88e1680_config()
607 res = genphy_config_aneg(phydev); in m88e1680_config()
612 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1680_config()
614 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1680_config()