Lines Matching refs:ioaddr
80 #define SROM_CLK_WRITE(data, ioaddr) do { \ argument
81 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
83 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
85 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
107 long ioaddr; /* I/O base address */ member
241 db->ioaddr = dev->iobase; in uli526x_initialize()
294 __FUNCTION__, db->ioaddr); in uli526x_init_one()
309 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, in uli526x_init_one()
342 if (!((inl(db->ioaddr + DCR12)) & 0x8)) { in uli526x_disable()
344 outl(ULI526X_RESET, db->ioaddr + DCR0); in uli526x_disable()
346 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); in uli526x_disable()
372 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */ in uli526x_init()
374 outl(db->cr0_data, db->ioaddr + DCR0); in uli526x_init()
382 phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id); in uli526x_init()
390 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr); in uli526x_init()
399 if (!(inl(db->ioaddr + DCR12) & 0x8)) { in uli526x_init()
401 phy_reg_reset = uli_phy_read(db->ioaddr, in uli526x_init()
404 uli_phy_write(db->ioaddr, db->phy_addr, 0, in uli526x_init()
416 uli526x_descriptor_init(db, db->ioaddr); in uli526x_init()
419 update_cr6(db->cr6_data, db->ioaddr); in uli526x_init()
423 outl(db->cr7_data, db->ioaddr + DCR7); in uli526x_init()
426 outl(db->cr15_data, db->ioaddr + DCR15); in uli526x_init()
430 update_cr6(db->cr6_data, db->ioaddr); in uli526x_init()
431 while (!(inl(db->ioaddr + DCR12) & 0x8)) in uli526x_init()
476 db->cr5_data = inl(db->ioaddr + DCR5); in uli526x_start_xmit()
477 outl(db->cr5_data, db->ioaddr + DCR5); in uli526x_start_xmit()
520 db->ioaddr); in uli526x_free_tx_pkt()
624 unsigned long ioaddr) in uli526x_descriptor_init() argument
636 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ in uli526x_descriptor_init()
644 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ in uli526x_descriptor_init()
692 static void update_cr6(u32 cr6_data, unsigned long ioaddr) in update_cr6() argument
695 outl(cr6_data, ioaddr + DCR6); in update_cr6()
732 static u16 read_srom_word(long ioaddr, int offset) in read_srom_word() argument
736 long cr9_ioaddr = ioaddr + DCR9; in read_srom_word()
778 phy_reg = uli_phy_read(db->ioaddr, in uli526x_set_phyxcer()
800 uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); in uli526x_set_phyxcer()
803 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); in uli526x_set_phyxcer()
815 unsigned long ioaddr; in uli_phy_write() local
822 ioaddr = iobase + DCR9; in uli_phy_write()
826 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); in uli_phy_write()
829 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); in uli_phy_write()
830 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); in uli_phy_write()
833 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); in uli_phy_write()
834 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); in uli_phy_write()
838 phy_write_1bit(ioaddr, phy_addr & i ? in uli_phy_write()
843 phy_write_1bit(ioaddr, offset & i ? in uli_phy_write()
847 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); in uli_phy_write()
848 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); in uli_phy_write()
852 phy_write_1bit(ioaddr, phy_data & i ? in uli_phy_write()
865 unsigned long ioaddr; in uli_phy_read() local
870 ioaddr = iobase + DCR9; in uli_phy_read()
874 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); in uli_phy_read()
877 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); in uli_phy_read()
878 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); in uli_phy_read()
881 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); in uli_phy_read()
882 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); in uli_phy_read()
886 phy_write_1bit(ioaddr, phy_addr & i ? in uli_phy_read()
891 phy_write_1bit(ioaddr, offset & i ? in uli_phy_read()
895 phy_read_1bit(ioaddr, chip_id); in uli_phy_read()
900 phy_data |= phy_read_1bit(ioaddr, chip_id); in uli_phy_read()
908 unsigned long ioaddr, cr10_value; in phy_readby_cr10() local
910 ioaddr = iobase + DCR10; in phy_readby_cr10()
914 outl(cr10_value, ioaddr); in phy_readby_cr10()
917 cr10_value = inl(ioaddr); in phy_readby_cr10()
927 unsigned long ioaddr, cr10_value; in phy_writeby_cr10() local
929 ioaddr = iobase + DCR10; in phy_writeby_cr10()
933 outl(cr10_value, ioaddr); in phy_writeby_cr10()
940 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) in phy_write_1bit() argument
942 outl(phy_data , ioaddr); /* MII Clock Low */ in phy_write_1bit()
944 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
946 outl(phy_data , ioaddr); /* MII Clock Low */ in phy_write_1bit()
954 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) in phy_read_1bit() argument
958 outl(0x50000 , ioaddr); in phy_read_1bit()
960 phy_data = (inl(ioaddr) >> 19) & 0x1; in phy_read_1bit()
961 outl(0x40000 , ioaddr); in phy_read_1bit()
976 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */ in set_mac_addr()
978 outl(0x1c0, db->ioaddr + DCR13); in set_mac_addr()
979 outl(0, db->ioaddr + DCR14); /* Clear reset port */ in set_mac_addr()
980 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */ in set_mac_addr()
981 outl(0, db->ioaddr + DCR14); /* Clear reset port */ in set_mac_addr()
982 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ in set_mac_addr()
984 outl(0x1b0, db->ioaddr + DCR13); in set_mac_addr()
988 outl(addr, db->ioaddr + DCR14); in set_mac_addr()
991 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ in set_mac_addr()
992 outl(0, db->ioaddr + DCR0); /* Clear CR0 */ in set_mac_addr()