226 	const struct tegra_pcie_soc *soc;  member
608 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_power_on()  local
636 	if (soc->has_cml_clk) {  in tegra_pcie_power_on()
655 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_pll_wait()  local
660 		value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_pll_wait()
670 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_phy_enable()  local
686 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
688 	value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;  in tegra_pcie_phy_enable()
689 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
692 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
694 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
699 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
701 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
726 	const struct tegra_pcie_soc *soc = pcie->soc;  local
742 	if (soc->has_pex_bias_ctrl)
756 	if (soc->has_gen2)
885 		ret = port->pcie->soc->afi_pex2_ctrl;
922 	const struct tegra_pcie_soc *soc = pcie->soc;  local
930 	if (pcie->soc->has_pex_clkreq_en)
939 	if (soc->force_pca_enable) {
946 	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
947 	if (soc->num_ports > 2)
948 		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
1099 	pcie->soc = &pci_tegra_soc[id];