174 	reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);  in comphy_pcie_power_up()
179 	reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);  in comphy_pcie_power_up()
184 	reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);  in comphy_pcie_power_up()
189 	reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);  in comphy_pcie_power_up()
194 	reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);  in comphy_pcie_power_up()
199 	reg_set16(phy_addr(PCIE, MISC_REG0),  in comphy_pcie_power_up()
213 		reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);  in comphy_pcie_power_up()
216 		reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);  in comphy_pcie_power_up()
222 	reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,  in comphy_pcie_power_up()
229 		reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);  in comphy_pcie_power_up()
232 		reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);  in comphy_pcie_power_up()
237 	reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0),  in comphy_pcie_power_up()
245 	ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1),	/* address */  in comphy_pcie_power_up()