Lines Matching refs:reg_set
205 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); in comphy_pcie_power_up()
265 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); in reg_set_indirect()
266 reg_set(rh_vsreg_data, data, mask); in reg_set_indirect()
314 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); in comphy_sata_power_up()
315 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); in comphy_sata_power_up()
321 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); in comphy_sata_power_up()
370 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); in comphy_usb3_power_up()
376 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); in comphy_usb3_power_up()
486 reg_set(rh_vsreg_addr, in comphy_usb3_power_up()
516 reg_set(USB32_CTRL_BASE, in comphy_usb3_power_up()
550 reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16), in comphy_usb2_power_up()
557 reg_set(USB2_PHY_CTRL_ADDR(usb32), in comphy_usb2_power_up()
564 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); in comphy_usb2_power_up()
569 reg_set(USB2_PHY_CHRGR_DET_ADDR, 0, in comphy_usb2_power_up()
624 reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); in comphy_emmc_power_up()
629 reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); in comphy_emmc_power_up()
634 reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); in comphy_emmc_power_up()
639 reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0); in comphy_emmc_power_up()
644 reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); in comphy_emmc_power_up()
645 reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000); in comphy_emmc_power_up()
650 reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); in comphy_emmc_power_up()
651 reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0); in comphy_emmc_power_up()
708 reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF); in comphy_sgmii_power_up()
716 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
724 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy); in comphy_sgmii_power_up()
731 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
737 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
842 reg_set(COMPHY_PHY_CFG1_ADDR(lane), in comphy_sgmii_power_up()
860 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle); in comphy_sgmii_power_up()
870 reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0); in comphy_sgmii_power_up()
882 reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF); in comphy_sgmii_power_up()