Lines Matching refs:data
73 u32 data; in polling_with_timeout() local
77 data = readl(addr) & mask; in polling_with_timeout()
78 } while (data != val && --usec_timout > 0); in polling_with_timeout()
81 return data; in polling_with_timeout()
90 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
138 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_pcie_power_up()
140 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_pcie_power_up()
142 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_pcie_power_up()
144 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
146 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; in comphy_pcie_power_up()
147 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
151 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_pcie_power_up()
153 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
154 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
162 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in comphy_pcie_power_up()
165 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in comphy_pcie_power_up()
168 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in comphy_pcie_power_up()
171 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in comphy_pcie_power_up()
172 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
174 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; in comphy_pcie_power_up()
177 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; in comphy_pcie_power_up()
179 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; in comphy_pcie_power_up()
182 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
185 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; in comphy_pcie_power_up()
192 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; in comphy_pcie_power_up()
193 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; in comphy_pcie_power_up()
195 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; in comphy_pcie_power_up()
198 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
210 data = 0; in comphy_pcie_power_up()
214 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; in comphy_pcie_power_up()
221 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; in comphy_pcie_power_up()
224 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; in comphy_pcie_power_up()
228 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_pcie_power_up()
232 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_pcie_power_up()
235 data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; in comphy_pcie_power_up()
236 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_pcie_power_up()
240 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_pcie_power_up()
244 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_pcie_power_up()
248 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_pcie_power_up()
249 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_pcie_power_up()
254 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; in comphy_pcie_power_up()
255 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in comphy_pcie_power_up()
270 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; in comphy_pcie_power_up()
273 data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; in comphy_pcie_power_up()
276 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; in comphy_pcie_power_up()
277 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in comphy_pcie_power_up()
281 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; in comphy_pcie_power_up()
284 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; in comphy_pcie_power_up()
285 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in comphy_pcie_power_up()
289 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; in comphy_pcie_power_up()
292 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; in comphy_pcie_power_up()
295 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; in comphy_pcie_power_up()
296 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
300 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; in comphy_pcie_power_up()
303 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; in comphy_pcie_power_up()
304 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_pcie_power_up()
309 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; in comphy_pcie_power_up()
312 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; in comphy_pcie_power_up()
315 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; in comphy_pcie_power_up()
316 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in comphy_pcie_power_up()
320 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; in comphy_pcie_power_up()
323 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; in comphy_pcie_power_up()
326 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; in comphy_pcie_power_up()
329 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; in comphy_pcie_power_up()
330 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_pcie_power_up()
334 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in comphy_pcie_power_up()
335 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_pcie_power_up()
339 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; in comphy_pcie_power_up()
340 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in comphy_pcie_power_up()
345 data = 0; in comphy_pcie_power_up()
346 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
350 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_pcie_power_up()
351 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_pcie_power_up()
355 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; in comphy_pcie_power_up()
356 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_pcie_power_up()
360 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_pcie_power_up()
361 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_pcie_power_up()
365 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; in comphy_pcie_power_up()
368 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; in comphy_pcie_power_up()
371 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in comphy_pcie_power_up()
372 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_pcie_power_up()
376 data = 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_pcie_power_up()
377 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_pcie_power_up()
383 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in comphy_pcie_power_up()
386 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_pcie_power_up()
387 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_pcie_power_up()
391 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in comphy_pcie_power_up()
392 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_pcie_power_up()
396 data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; in comphy_pcie_power_up()
398 data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; in comphy_pcie_power_up()
400 data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; in comphy_pcie_power_up()
401 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in comphy_pcie_power_up()
403 data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; in comphy_pcie_power_up()
404 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in comphy_pcie_power_up()
408 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; in comphy_pcie_power_up()
410 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; in comphy_pcie_power_up()
412 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; in comphy_pcie_power_up()
413 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_pcie_power_up()
417 data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; in comphy_pcie_power_up()
418 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in comphy_pcie_power_up()
422 data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; in comphy_pcie_power_up()
423 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_pcie_power_up()
427 data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_pcie_power_up()
428 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_pcie_power_up()
432 data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; in comphy_pcie_power_up()
433 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in comphy_pcie_power_up()
437 data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; in comphy_pcie_power_up()
439 data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; in comphy_pcie_power_up()
441 data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; in comphy_pcie_power_up()
442 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in comphy_pcie_power_up()
447 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; in comphy_pcie_power_up()
448 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); in comphy_pcie_power_up()
504 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in comphy_pcie_power_up()
505 mask = data; in comphy_pcie_power_up()
506 data = polling_with_timeout(addr, data, mask, 15000); in comphy_pcie_power_up()
507 if (data != 0) { in comphy_pcie_power_up()
510 data); in comphy_pcie_power_up()
524 u32 mask, data, ret = 1; in comphy_usb3_power_up() local
533 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_usb3_power_up()
535 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_usb3_power_up()
537 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_usb3_power_up()
539 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
541 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; in comphy_usb3_power_up()
542 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
546 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_usb3_power_up()
548 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
549 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
558 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in comphy_usb3_power_up()
561 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in comphy_usb3_power_up()
564 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in comphy_usb3_power_up()
567 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in comphy_usb3_power_up()
568 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_usb3_power_up()
579 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_usb3_power_up()
582 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_usb3_power_up()
583 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_usb3_power_up()
609 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; in comphy_usb3_power_up()
612 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; in comphy_usb3_power_up()
615 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; in comphy_usb3_power_up()
616 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_usb3_power_up()
629 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in comphy_usb3_power_up()
630 mask = data; in comphy_usb3_power_up()
631 data = polling_with_timeout(addr, data, mask, 15000); in comphy_usb3_power_up()
632 if (data != 0) { in comphy_usb3_power_up()
634 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); in comphy_usb3_power_up()
646 u32 mask, data, i, ret = 1; in comphy_sata_power_up() local
691 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; in comphy_sata_power_up()
694 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; in comphy_sata_power_up()
697 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; in comphy_sata_power_up()
700 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; in comphy_sata_power_up()
701 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
706 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sata_power_up()
708 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sata_power_up()
710 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_sata_power_up()
712 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_sata_power_up()
713 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sata_power_up()
722 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sata_power_up()
724 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sata_power_up()
725 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sata_power_up()
738 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sata_power_up()
741 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sata_power_up()
742 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sata_power_up()
755 data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
757 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sata_power_up()
759 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
761 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
763 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
764 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sata_power_up()
767 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in comphy_sata_power_up()
769 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in comphy_sata_power_up()
771 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in comphy_sata_power_up()
773 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; in comphy_sata_power_up()
775 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_sata_power_up()
776 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sata_power_up()
780 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
782 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; in comphy_sata_power_up()
784 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
786 data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
788 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
789 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_sata_power_up()
793 data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
795 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; in comphy_sata_power_up()
797 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
799 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
801 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; in comphy_sata_power_up()
803 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
805 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in comphy_sata_power_up()
806 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_sata_power_up()
810 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; in comphy_sata_power_up()
812 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; in comphy_sata_power_up()
814 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sata_power_up()
816 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; in comphy_sata_power_up()
818 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; in comphy_sata_power_up()
820 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; in comphy_sata_power_up()
822 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; in comphy_sata_power_up()
823 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sata_power_up()
827 data = 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_sata_power_up()
828 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
830 data = 0x0 << HPIPE_SMAPLER_OFFSET; in comphy_sata_power_up()
831 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
835 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_sata_power_up()
836 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sata_power_up()
840 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_sata_power_up()
841 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sata_power_up()
845 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_sata_power_up()
847 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_sata_power_up()
848 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sata_power_up()
852 data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; in comphy_sata_power_up()
854 data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; in comphy_sata_power_up()
856 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; in comphy_sata_power_up()
858 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in comphy_sata_power_up()
860 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_sata_power_up()
861 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_sata_power_up()
865 data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; in comphy_sata_power_up()
866 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_sata_power_up()
870 data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; in comphy_sata_power_up()
872 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; in comphy_sata_power_up()
873 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
875 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; in comphy_sata_power_up()
876 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
878 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; in comphy_sata_power_up()
879 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
883 data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; in comphy_sata_power_up()
885 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
887 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sata_power_up()
889 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
890 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sata_power_up()
894 data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; in comphy_sata_power_up()
896 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
898 data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; in comphy_sata_power_up()
900 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
901 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in comphy_sata_power_up()
905 data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; in comphy_sata_power_up()
907 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
909 data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; in comphy_sata_power_up()
911 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
913 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; in comphy_sata_power_up()
915 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; in comphy_sata_power_up()
916 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in comphy_sata_power_up()
920 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; in comphy_sata_power_up()
921 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sata_power_up()
948 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; in comphy_sata_power_up()
951 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; in comphy_sata_power_up()
954 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; in comphy_sata_power_up()
957 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; in comphy_sata_power_up()
958 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
971 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & in comphy_sata_power_up()
973 mask = data; in comphy_sata_power_up()
974 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sata_power_up()
975 if (data != 0) { in comphy_sata_power_up()
977 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); in comphy_sata_power_up()
979 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), in comphy_sata_power_up()
980 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); in comphy_sata_power_up()
992 u32 mask, data, ret = 1; in comphy_sgmii_power_up() local
1002 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sgmii_power_up()
1004 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sgmii_power_up()
1005 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sgmii_power_up()
1009 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sgmii_power_up()
1013 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sgmii_power_up()
1014 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sgmii_power_up()
1017 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sgmii_power_up()
1018 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sgmii_power_up()
1021 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sgmii_power_up()
1023 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sgmii_power_up()
1025 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_sgmii_power_up()
1026 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1030 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1032 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sgmii_power_up()
1034 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1035 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1039 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1041 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sgmii_power_up()
1042 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1052 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_sgmii_power_up()
1053 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sgmii_power_up()
1056 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sgmii_power_up()
1058 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sgmii_power_up()
1059 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sgmii_power_up()
1062 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in comphy_sgmii_power_up()
1063 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sgmii_power_up()
1066 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_sgmii_power_up()
1068 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_sgmii_power_up()
1069 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sgmii_power_up()
1072 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sgmii_power_up()
1073 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sgmii_power_up()
1085 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sgmii_power_up()
1087 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sgmii_power_up()
1089 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sgmii_power_up()
1090 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1094 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_sgmii_power_up()
1096 mask = data; in comphy_sgmii_power_up()
1097 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sgmii_power_up()
1098 if (data != 0) { in comphy_sgmii_power_up()
1100 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1102 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_sgmii_power_up()
1103 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_sgmii_power_up()
1109 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sgmii_power_up()
1110 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1114 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_sgmii_power_up()
1115 mask = data; in comphy_sgmii_power_up()
1116 data = polling_with_timeout(addr, data, mask, 100); in comphy_sgmii_power_up()
1117 if (data != 0) { in comphy_sgmii_power_up()
1118 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1126 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sgmii_power_up()
1128 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1129 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1138 u32 mask, data, ret = 1; in comphy_sfi_power_up() local
1148 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sfi_power_up()
1150 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sfi_power_up()
1151 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sfi_power_up()
1155 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sfi_power_up()
1157 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sfi_power_up()
1159 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sfi_power_up()
1161 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sfi_power_up()
1163 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sfi_power_up()
1165 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_sfi_power_up()
1166 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1170 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sfi_power_up()
1172 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sfi_power_up()
1174 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sfi_power_up()
1175 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1178 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sfi_power_up()
1180 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sfi_power_up()
1181 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1191 data = (speed == PHY_SPEED_5_15625G) ? in comphy_sfi_power_up()
1195 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_sfi_power_up()
1196 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sfi_power_up()
1199 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sfi_power_up()
1201 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sfi_power_up()
1202 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sfi_power_up()
1205 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in comphy_sfi_power_up()
1206 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sfi_power_up()
1209 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_sfi_power_up()
1211 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_sfi_power_up()
1212 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sfi_power_up()
1215 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sfi_power_up()
1216 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sfi_power_up()
1221 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1223 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1225 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1227 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1230 data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1232 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in comphy_sfi_power_up()
1238 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; in comphy_sfi_power_up()
1239 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sfi_power_up()
1242 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_sfi_power_up()
1243 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sfi_power_up()
1247 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sfi_power_up()
1250 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; in comphy_sfi_power_up()
1252 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sfi_power_up()
1254 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sfi_power_up()
1257 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; in comphy_sfi_power_up()
1259 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; in comphy_sfi_power_up()
1260 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in comphy_sfi_power_up()
1263 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; in comphy_sfi_power_up()
1265 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; in comphy_sfi_power_up()
1266 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in comphy_sfi_power_up()
1269 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in comphy_sfi_power_up()
1271 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; in comphy_sfi_power_up()
1272 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in comphy_sfi_power_up()
1275 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in comphy_sfi_power_up()
1276 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in comphy_sfi_power_up()
1279 data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in comphy_sfi_power_up()
1282 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sfi_power_up()
1284 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sfi_power_up()
1287 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sfi_power_up()
1289 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sfi_power_up()
1291 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; in comphy_sfi_power_up()
1293 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; in comphy_sfi_power_up()
1295 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in comphy_sfi_power_up()
1297 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sfi_power_up()
1301 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_sfi_power_up()
1303 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_sfi_power_up()
1304 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sfi_power_up()
1308 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in comphy_sfi_power_up()
1309 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_sfi_power_up()
1312 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; in comphy_sfi_power_up()
1316 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in comphy_sfi_power_up()
1318 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in comphy_sfi_power_up()
1320 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in comphy_sfi_power_up()
1322 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sfi_power_up()
1326 data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; in comphy_sfi_power_up()
1327 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_sfi_power_up()
1331 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in comphy_sfi_power_up()
1332 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1336 data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; in comphy_sfi_power_up()
1337 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in comphy_sfi_power_up()
1341 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in comphy_sfi_power_up()
1342 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_sfi_power_up()
1346 data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; in comphy_sfi_power_up()
1348 data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; in comphy_sfi_power_up()
1349 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_sfi_power_up()
1353 data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; in comphy_sfi_power_up()
1354 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1358 data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; in comphy_sfi_power_up()
1359 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in comphy_sfi_power_up()
1363 data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; in comphy_sfi_power_up()
1364 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in comphy_sfi_power_up()
1368 data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; in comphy_sfi_power_up()
1370 data |= 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_sfi_power_up()
1371 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1373 data = 0x0 << HPIPE_SMAPLER_OFFSET; in comphy_sfi_power_up()
1374 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1378 data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_sfi_power_up()
1379 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sfi_power_up()
1384 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sfi_power_up()
1386 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sfi_power_up()
1388 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sfi_power_up()
1389 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1394 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_sfi_power_up()
1396 mask = data; in comphy_sfi_power_up()
1397 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sfi_power_up()
1398 if (data != 0) { in comphy_sfi_power_up()
1399 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1401 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_sfi_power_up()
1402 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_sfi_power_up()
1408 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sfi_power_up()
1409 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1414 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_sfi_power_up()
1415 mask = data; in comphy_sfi_power_up()
1416 data = polling_with_timeout(addr, data, mask, 100); in comphy_sfi_power_up()
1417 if (data != 0) { in comphy_sfi_power_up()
1419 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1427 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sfi_power_up()
1429 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sfi_power_up()
1430 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1439 u32 mask, data, ret = 1; in comphy_rxauii_power_up() local
1449 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_rxauii_power_up()
1451 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_rxauii_power_up()
1452 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_rxauii_power_up()
1467 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_rxauii_power_up()
1469 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_rxauii_power_up()
1471 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_rxauii_power_up()
1473 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_rxauii_power_up()
1475 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_rxauii_power_up()
1477 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_rxauii_power_up()
1479 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; in comphy_rxauii_power_up()
1480 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1484 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1486 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_rxauii_power_up()
1488 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1489 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1492 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1494 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_rxauii_power_up()
1495 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1508 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_rxauii_power_up()
1510 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_rxauii_power_up()
1511 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_rxauii_power_up()
1517 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_rxauii_power_up()
1519 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_rxauii_power_up()
1520 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_rxauii_power_up()
1541 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_rxauii_power_up()
1543 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_rxauii_power_up()
1545 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in comphy_rxauii_power_up()
1546 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_rxauii_power_up()
1549 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_rxauii_power_up()
1551 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_rxauii_power_up()
1552 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_rxauii_power_up()
1556 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in comphy_rxauii_power_up()
1557 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_rxauii_power_up()
1562 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_rxauii_power_up()
1564 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_rxauii_power_up()
1566 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_rxauii_power_up()
1567 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1572 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_rxauii_power_up()
1574 mask = data; in comphy_rxauii_power_up()
1575 data = polling_with_timeout(addr, data, mask, 15000); in comphy_rxauii_power_up()
1576 if (data != 0) { in comphy_rxauii_power_up()
1578 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_rxauii_power_up()
1580 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_rxauii_power_up()
1581 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_rxauii_power_up()
1592 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_rxauii_power_up()
1593 mask = data; in comphy_rxauii_power_up()
1594 data = polling_with_timeout(addr, data, mask, 100); in comphy_rxauii_power_up()
1595 if (data != 0) { in comphy_rxauii_power_up()
1597 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_rxauii_power_up()
1605 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_rxauii_power_up()
1607 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1608 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1619 u32 mask, data; in comphy_utmi_power_down() local
1637 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; in comphy_utmi_power_down()
1640 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; in comphy_utmi_power_down()
1641 reg_set(usb_cfg_addr, data, mask); in comphy_utmi_power_down()
1646 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; in comphy_utmi_power_down()
1649 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; in comphy_utmi_power_down()
1650 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); in comphy_utmi_power_down()
1664 u32 mask, data; in comphy_utmi_phy_config() local
1670 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; in comphy_utmi_phy_config()
1673 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; in comphy_utmi_phy_config()
1676 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; in comphy_utmi_phy_config()
1677 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1686 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; in comphy_utmi_phy_config()
1689 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; in comphy_utmi_phy_config()
1690 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1694 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; in comphy_utmi_phy_config()
1697 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; in comphy_utmi_phy_config()
1698 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); in comphy_utmi_phy_config()
1702 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; in comphy_utmi_phy_config()
1705 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; in comphy_utmi_phy_config()
1706 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); in comphy_utmi_phy_config()
1710 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; in comphy_utmi_phy_config()
1713 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; in comphy_utmi_phy_config()
1714 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1724 u32 data, mask, ret = 1; in comphy_utmi_power_up() local
1740 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; in comphy_utmi_power_up()
1741 mask = data; in comphy_utmi_power_up()
1742 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1743 if (data != 0) { in comphy_utmi_power_up()
1745 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1749 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; in comphy_utmi_power_up()
1750 mask = data; in comphy_utmi_power_up()
1751 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1752 if (data != 0) { in comphy_utmi_power_up()
1754 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1759 data = UTMI_PLL_CTRL_PLL_RDY_MASK; in comphy_utmi_power_up()
1760 mask = data; in comphy_utmi_power_up()
1761 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1762 if (data != 0) { in comphy_utmi_power_up()
1764 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()