Lines Matching refs:pctl
27 struct rk3368_ddr_pctl *pctl; member
192 static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) in send_command() argument
197 writel(mcmd, &pctl->mcmd); in send_command()
198 while (readl(&pctl->mcmd) & START_CMD) in send_command()
202 static void send_mrs(struct rk3368_ddr_pctl *pctl, in send_mrs() argument
208 writel(mcmd, &pctl->mcmd); in send_mrs()
209 while (readl(&pctl->mcmd) & START_CMD) in send_mrs()
213 static int memory_init(struct rk3368_ddr_pctl *pctl, in memory_init() argument
225 writel(POWER_UP_START, &pctl->powctl); in memory_init()
234 } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); in memory_init()
248 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD); in memory_init()
250 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); in memory_init()
251 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]); in memory_init()
252 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]); in memory_init()
253 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]); in memory_init()
254 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]); in memory_init()
255 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD); in memory_init()
260 static void move_to_config_state(struct rk3368_ddr_pctl *pctl) in move_to_config_state() argument
266 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_config_state()
270 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
271 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_config_state()
277 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
278 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_config_state()
290 static void move_to_access_state(struct rk3368_ddr_pctl *pctl) in move_to_access_state() argument
296 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_access_state()
300 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & in move_to_access_state()
304 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
305 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_access_state()
310 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
311 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_access_state()
316 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
317 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) in move_to_access_state()
398 static int dfi_cfg(struct rk3368_ddr_pctl *pctl) in dfi_cfg() argument
403 writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); in dfi_cfg()
406 &pctl->dfistcfg1); in dfi_cfg()
407 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
409 &pctl->dfilpcfg0); in dfi_cfg()
411 writel(1, &pctl->dfitphyupdtype0); in dfi_cfg()
413 writel(0x1f, &pctl->dfitphyrdlat); in dfi_cfg()
414 writel(0, &pctl->dfitphywrdata); in dfi_cfg()
415 writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */ in dfi_cfg()
417 setbits_le32(&pctl->dfistcfg0, DFI_INIT_START); in dfi_cfg()
426 } while ((readl(&pctl->dfiststat0) & 1) == 0); in dfi_cfg()
544 static void pctl_cfg(struct rk3368_ddr_pctl *pctl, in pctl_cfg() argument
550 copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, in pctl_cfg()
552 writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); in pctl_cfg()
555 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg); in pctl_cfg()
556 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in pctl_cfg()
559 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
560 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
563 writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg); in pctl_cfg()
566 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); in pctl_cfg()
569 static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl, in ddrphy_data_training() argument
572 const u32 trefi = readl(&pctl->trefi); in ddrphy_data_training()
577 writel(0 | BIT(31), &pctl->trefi); in ddrphy_data_training()
591 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); in ddrphy_data_training()
594 writel(trefi | BIT(31), &pctl->trefi); in ddrphy_data_training()
603 struct rk3368_ddr_pctl *pctl = priv->pctl; in sdram_col_row_detect() local
609 move_to_config_state(pctl); in sdram_col_row_detect()
611 move_to_access_state(pctl); in sdram_col_row_detect()
629 move_to_config_state(pctl); in sdram_col_row_detect()
631 move_to_access_state(pctl); in sdram_col_row_detect()
798 struct rk3368_ddr_pctl *pctl = priv->pctl; in setup_sdram() local
820 dfi_cfg(pctl); in setup_sdram()
827 pctl_cfg(pctl, params, grf); in setup_sdram()
835 ret = memory_init(pctl, params); in setup_sdram()
839 move_to_config_state(pctl); in setup_sdram()
841 ddrphy_data_training(pctl, ddrphy); in setup_sdram()
842 move_to_access_state(pctl); in setup_sdram()
906 struct rk3368_ddr_pctl *pctl; in rk3368_dmc_probe() local
926 pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0]; in rk3368_dmc_probe()
931 priv->pctl = pctl; in rk3368_dmc_probe()