Lines Matching refs:pctl
28 struct rk3288_ddr_pctl *pctl; member
172 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
174 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
176 &pctl->dfistcfg1); in dfi_cfg()
177 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
179 &pctl->dfilpcfg0); in dfi_cfg()
181 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
182 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
183 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
184 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
185 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); in dfi_cfg()
186 writel(1, &pctl->dfitphyupdtype0); in dfi_cfg()
190 &pctl->dfiodtcfg); in dfi_cfg()
192 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in dfi_cfg()
194 writel(0, &pctl->dfiupdcfg); in dfi_cfg()
226 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, in pctl_cfg() argument
230 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
236 &pctl->dfitrddataen); in pctl_cfg()
239 &pctl->dfitrddataen); in pctl_cfg()
242 &pctl->dfitphywrlat); in pctl_cfg()
246 &pctl->mcfg); in pctl_cfg()
252 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
309 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
312 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
314 while (readl(&pctl->mcmd) & START_CMD) in send_command()
318 static inline void send_command_op(struct rk3288_ddr_pctl *pctl, in send_command_op() argument
321 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
339 struct rk3288_ddr_pctl *pctl) in move_to_config_state() argument
344 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_config_state()
348 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
349 while ((readl(&pctl->stat) & PCTL_STAT_MSK) in move_to_config_state()
364 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
365 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_config_state()
379 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio() local
384 setbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
394 clrbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
411 setbits_le32(&pctl->dfistcfg0, 1 << 2); in set_bandwidth_ratio()
423 struct rk3288_ddr_pctl *pctl = chan->pctl; in data_training() local
426 writel(0, &pctl->trefi); in data_training()
450 if (!(readl(&pctl->ppcfg) & 1)) { in data_training()
466 send_command(pctl, rank, REF_CMD, 0); in data_training()
472 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
480 struct rk3288_ddr_pctl *pctl = chan->pctl; in move_to_access_state() local
484 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_access_state()
488 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & in move_to_access_state()
492 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
493 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_access_state()
501 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
502 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_access_state()
506 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
507 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) in move_to_access_state()
631 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_col_row_detect() local
654 move_to_config_state(publ, pctl); in sdram_col_row_detect()
730 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_init() local
736 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
738 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
744 writel(POWER_UP_START, &pctl->powctl); in sdram_init()
745 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) in sdram_init()
749 move_to_config_state(publ, pctl); in sdram_init()
778 writel(0, &pctl->mrrcfg0); in sdram_init()
780 send_command_op(pctl, 1, MRR_CMD, i, 0); in sdram_init()
900 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3188_dmc_probe()