Lines Matching refs:pctl
27 struct rk322x_ddr_pctl *pctl; member
153 static void send_command(struct rk322x_ddr_pctl *pctl, in send_command() argument
156 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
158 while (readl(&pctl->mcmd) & START_CMD) in send_command()
165 struct rk322x_ddr_pctl *pctl = chan->pctl; in memory_init() local
169 send_command(pctl, 3, DESELECT_CMD, 0); in memory_init()
171 send_command(pctl, 3, PREA_CMD, 0); in memory_init()
172 send_command(pctl, 3, MRS_CMD, in memory_init()
177 send_command(pctl, 3, MRS_CMD, in memory_init()
182 send_command(pctl, 3, MRS_CMD, in memory_init()
187 send_command(pctl, 3, MRS_CMD, in memory_init()
193 send_command(pctl, 3, ZQCL_CMD, 0); in memory_init()
195 send_command(pctl, 3, MRS_CMD, in memory_init()
200 send_command(pctl, 3, MRS_CMD, in memory_init()
205 send_command(pctl, 3, MRS_CMD, in memory_init()
210 send_command(pctl, 3, MRS_CMD, in memory_init()
214 send_command(pctl, 3, MRS_CMD, in memory_init()
218 send_command(pctl, 3, MRS_CMD, in memory_init()
223 send_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) << in memory_init()
233 struct rk322x_ddr_pctl *pctl = chan->pctl; in data_training() local
239 value = readl(&pctl->trefi) | (1 << 31); in data_training()
240 writel(1 << 31, &pctl->trefi); in data_training()
256 send_command(pctl, 3, PREA_CMD, 0); in data_training()
257 send_command(pctl, 3, REF_CMD, 0); in data_training()
259 writel(value, &pctl->trefi); in data_training()
270 static void move_to_config_state(struct rk322x_ddr_pctl *pctl) in move_to_config_state() argument
275 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_config_state()
278 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
279 while ((readl(&pctl->stat) & PCTL_STAT_MASK) in move_to_config_state()
289 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
290 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_config_state()
301 static void move_to_access_state(struct rk322x_ddr_pctl *pctl) in move_to_access_state() argument
306 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_access_state()
309 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
310 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_access_state()
314 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
315 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_access_state()
319 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
320 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_access_state()
331 static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl) in move_to_lowpower_state() argument
336 state = readl(&pctl->stat) & PCTL_STAT_MASK; in move_to_lowpower_state()
339 writel(CFG_STATE, &pctl->sctl); in move_to_lowpower_state()
340 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) in move_to_lowpower_state()
344 writel(GO_STATE, &pctl->sctl); in move_to_lowpower_state()
345 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) in move_to_lowpower_state()
349 writel(SLEEP_STATE, &pctl->sctl); in move_to_lowpower_state()
350 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != in move_to_lowpower_state()
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw() local
385 setbits_le32(&pctl->ppcfg, 1); in set_bw()
391 clrbits_le32(&pctl->ppcfg, 1); in set_bw()
400 static void pctl_cfg(struct rk322x_ddr_pctl *pctl, in pctl_cfg() argument
413 writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); in pctl_cfg()
414 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); in pctl_cfg()
415 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in pctl_cfg()
416 writel(0x51010, &pctl->dfilpcfg0); in pctl_cfg()
418 writel(1, &pctl->dfitphyupdtype0); in pctl_cfg()
419 writel(0x0d, &pctl->dfitphyrdlat); in pctl_cfg()
420 writel(0, &pctl->dfitphywrdata); in pctl_cfg()
422 writel(0, &pctl->dfiupdcfg); in pctl_cfg()
423 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
427 &pctl->dfiodtcfg); in pctl_cfg()
428 writel(7 << 16, &pctl->dfiodtcfg1); in pctl_cfg()
429 writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
430 writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
431 writel(500, &pctl->trsth); in pctl_cfg()
435 &pctl->mcfg); in pctl_cfg()
443 writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
444 writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat); in pctl_cfg()
445 writel(0, &pctl->trsth); in pctl_cfg()
451 &pctl->mcfg); in pctl_cfg()
452 writel(0, &pctl->dfiodtcfg); in pctl_cfg()
453 writel(0, &pctl->dfiodtcfg1); in pctl_cfg()
459 &pctl->mcfg); in pctl_cfg()
460 writel((1 << 3) | (1 << 2), &pctl->dfiodtcfg); in pctl_cfg()
461 writel((7 << 16) | 4, &pctl->dfiodtcfg1); in pctl_cfg()
465 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
539 move_to_config_state(chan->pctl); in dram_cfg_rbc()
574 move_to_access_state(chan->pctl); in dram_cfg_rbc()
612 move_to_config_state(dram->chan[0].pctl); in dram_cap_detect()
620 move_to_lowpower_state(dram->chan[0].pctl); in dram_cap_detect()
622 move_to_config_state(dram->chan[0].pctl); in dram_cap_detect()
635 move_to_access_state(dram->chan[0].pctl); in dram_cap_detect()
699 pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf); in sdram_init()
701 writel(POWER_UP_START, &dram->chan[0].pctl->powctl); in sdram_init()
702 while (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE)) in sdram_init()
705 move_to_access_state(dram->chan[0].pctl); in sdram_init()
797 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk322x_dmc_probe()