163 			struct rk322x_sdram_params *sdram_params)  in memory_init()  argument
166 	u32 dramtype = sdram_params->base.dramtype;  in memory_init()
174 			     (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) <<  in memory_init()
179 			     (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) <<  in memory_init()
184 			     (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) <<  in memory_init()
189 			     ((sdram_params->phy_timing.mr[0] |  in memory_init()
212 			     (sdram_params->phy_timing.mr[1] &  in memory_init()
216 			     (sdram_params->phy_timing.mr[2] &  in memory_init()
220 			     (sdram_params->phy_timing.mr[3] &  in memory_init()
225 				     (sdram_params->phy_timing.mr11 &  in memory_init()
401 		     struct rk322x_sdram_params *sdram_params,  in pctl_cfg()  argument
406 	u32 dramtype = sdram_params->base.dramtype;  in pctl_cfg()
408 	if (sdram_params->ch[0].bw == 2)  in pctl_cfg()
423 	copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,  in pctl_cfg()
438 		if (sdram_params->phy_timing.bl & PHT_BL_8)  in pctl_cfg()
469 		    struct rk322x_sdram_params *sdram_params)  in phy_cfg()  argument
473 	struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing;  in phy_cfg()
474 	struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing;  in phy_cfg()
475 	struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing;  in phy_cfg()
484 	switch (sdram_params->base.dramtype) {  in phy_cfg()
502 	if (sdram_params->base.dramtype == LPDDR2)  in phy_cfg()
532 		  struct rk322x_sdram_params *sdram_params)  in dram_cfg_rbc()  argument
536 	struct rk322x_sdram_channel *config = &sdram_params->ch[0];  in dram_cfg_rbc()
578 			    struct rk322x_sdram_params *sdram_params)  in dram_all_config()  argument
580 	struct rk322x_sdram_channel *info = &sdram_params->ch[0];  in dram_all_config()
583 	sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;  in dram_all_config()
601 			   struct rk322x_sdram_params *sdram_params)  in dram_cap_detect()  argument
607 	if (sdram_params->base.dramtype == DDR3)  in dram_cap_detect()
608 		sdram_params->ch[0].dbw = 1;  in dram_cap_detect()
610 		sdram_params->ch[0].dbw = 2;  in dram_cap_detect()
628 	sdram_params->ch[0].bw = bw;  in dram_cap_detect()
629 	sdram_params->ch[0].bk = 3;  in dram_cap_detect()
650 		sdram_params->ch[0].col = col;  in dram_cap_detect()
668 		sdram_params->ch[0].cs1_row = row;  in dram_cap_detect()
669 		sdram_params->ch[0].row_3_4 = 0;  in dram_cap_detect()
670 		sdram_params->ch[0].cs0_row = row;  in dram_cap_detect()
678 		sdram_params->ch[0].rank = 2;  in dram_cap_detect()
680 		sdram_params->ch[0].rank = 1;  in dram_cap_detect()
686 		      struct rk322x_sdram_params *sdram_params)  in sdram_init()  argument
691 			   sdram_params->base.ddr_freq * MHz * 2);  in sdram_init()
698 	phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq);  in sdram_init()
699 	pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf);  in sdram_init()
700 	phy_cfg(&dram->chan[0], sdram_params);  in sdram_init()
704 	memory_init(&dram->chan[0], sdram_params);  in sdram_init()
706 	ret = dram_cap_detect(dram, sdram_params);  in sdram_init()
709 	dram_cfg_rbc(&dram->chan[0], sdram_params);  in sdram_init()
710 	dram_all_config(dram, sdram_params);  in sdram_init()