589 static void dram_all_config(const struct dram_info *dram,  in dram_all_config()  argument
611 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);  in dram_all_config()
613 	writel(sys_reg, &dram->pmu->sys_reg[2]);  in dram_all_config()
614 	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);  in dram_all_config()
617 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,  in sdram_rank_bw_detect()  argument
622 	const struct chan_info *chan = &dram->chan[channel];  in sdram_rank_bw_detect()
648 					    dram->grf);  in sdram_rank_bw_detect()
658 			ddr_phy_ctl_reset(dram->cru, channel, 1);  in sdram_rank_bw_detect()
660 			ddr_phy_ctl_reset(dram->cru, channel, 0);  in sdram_rank_bw_detect()
670 static int sdram_col_row_detect(struct dram_info *dram, int channel,  in sdram_col_row_detect()  argument
675 	const struct chan_info *chan = &dram->chan[channel];  in sdram_col_row_detect()
780 static int sdram_init(struct dram_info *dram,  in sdram_init()  argument
797 	ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);  in sdram_init()
805 		const struct chan_info *chan = &dram->chan[channel];  in sdram_init()
811 			rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17);  in sdram_init()
813 			rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a);  in sdram_init()
814 		phy_pctrl_reset(dram->cru, publ, channel);  in sdram_init()
819 		pctl_cfg(channel, pctl, sdram_params, dram->grf);  in sdram_init()
853 				    sdram_params->ch[channel].bw, dram->grf);  in sdram_init()
890 		sdram_rank_bw_detect(dram, channel, sdram_params);  in sdram_init()
903 		ret = sdram_col_row_detect(dram, channel, sdram_params);  in sdram_init()
916 	dram_all_config(dram, sdram_params);  in sdram_init()