Lines Matching refs:pctl
30 struct rk3288_ddr_pctl *pctl; member
171 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
173 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
175 &pctl->dfistcfg1); in dfi_cfg()
176 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
178 &pctl->dfilpcfg0); in dfi_cfg()
180 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
181 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
182 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
183 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
184 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); in dfi_cfg()
185 writel(1, &pctl->dfitphyupdtype0); in dfi_cfg()
189 &pctl->dfiodtcfg); in dfi_cfg()
191 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in dfi_cfg()
193 writel(0, &pctl->dfiupdcfg); in dfi_cfg()
239 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, in pctl_cfg() argument
246 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
251 &pctl->dfitrddataen); in pctl_cfg()
253 &pctl->dfitphywrlat); in pctl_cfg()
259 &pctl->mcfg); in pctl_cfg()
268 &pctl->dfitrddataen); in pctl_cfg()
271 &pctl->dfitrddataen); in pctl_cfg()
274 &pctl->dfitphywrlat); in pctl_cfg()
278 &pctl->mcfg); in pctl_cfg()
286 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
367 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
370 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
372 while (readl(&pctl->mcmd) & START_CMD) in send_command()
376 static inline void send_command_op(struct rk3288_ddr_pctl *pctl, in send_command_op() argument
379 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
397 struct rk3288_ddr_pctl *pctl) in move_to_config_state() argument
402 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_config_state()
406 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
407 while ((readl(&pctl->stat) & PCTL_STAT_MSK) in move_to_config_state()
422 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
423 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_config_state()
437 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio() local
442 setbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
452 clrbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
469 setbits_le32(&pctl->dfistcfg0, 1 << 2); in set_bandwidth_ratio()
481 struct rk3288_ddr_pctl *pctl = chan->pctl; in data_training() local
484 writel(0, &pctl->trefi); in data_training()
508 if (!(readl(&pctl->ppcfg) & 1)) { in data_training()
524 send_command(pctl, rank, REF_CMD, 0); in data_training()
530 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
538 struct rk3288_ddr_pctl *pctl = chan->pctl; in move_to_access_state() local
542 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_access_state()
546 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & in move_to_access_state()
550 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
551 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_access_state()
559 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
560 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_access_state()
563 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
564 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) in move_to_access_state()
676 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_col_row_detect() local
698 move_to_config_state(publ, pctl); in sdram_col_row_detect()
806 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_init() local
817 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
819 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
825 writel(POWER_UP_START, &pctl->powctl); in sdram_init()
826 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) in sdram_init()
830 move_to_config_state(publ, pctl); in sdram_init()
833 send_command(pctl, 3, DESELECT_CMD, 0); in sdram_init()
835 send_command(pctl, 3, PREA_CMD, 0); in sdram_init()
837 send_command_op(pctl, 3, MRS_CMD, 63, 0xfc); in sdram_init()
839 send_command_op(pctl, 3, MRS_CMD, 1, in sdram_init()
842 send_command_op(pctl, 3, MRS_CMD, 2, in sdram_init()
845 send_command_op(pctl, 3, MRS_CMD, 3, in sdram_init()
874 send_command_op(pctl, in sdram_init()
879 writel(0, &pctl->mrrcfg0); in sdram_init()
880 send_command_op(pctl, 1, MRR_CMD, 8, 0); in sdram_init()
882 if ((readl(&pctl->mrrstat0) & 0x3) != 3) { in sdram_init()
894 writel(0, &pctl->mrrcfg0); in sdram_init()
896 send_command_op(pctl, 1, MRR_CMD, i, 0); in sdram_init()
1063 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3288_dmc_probe()
1065 priv->chan[1].pctl = regmap_get_range(plat->map, 2); in rk3288_dmc_probe()