Lines Matching refs:sdram_params
240 struct rk3288_sdram_params *sdram_params, in pctl_cfg() argument
245 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; in pctl_cfg()
246 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
247 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
248 switch (sdram_params->base.dramtype) { in pctl_cfg()
250 writel(sdram_params->pctl_timing.tcl - 1, in pctl_cfg()
252 writel(sdram_params->pctl_timing.tcwl, in pctl_cfg()
263 sdram_params->base.odt); in pctl_cfg()
266 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
267 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
270 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
273 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
290 struct rk3288_sdram_params *sdram_params) in phy_cfg() argument
294 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
300 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
301 sizeof(sdram_params->phy_timing)); in phy_cfg()
302 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
304 writel(sdram_params->base.noc_activate, &msch->activate); in phy_cfg()
317 switch (sdram_params->base.dramtype) { in phy_cfg()
345 if (sdram_params->base.odt) { in phy_cfg()
473 struct rk3288_sdram_params *sdram_params) in data_training() argument
486 if (sdram_params->base.dramtype != LPDDR3) in data_training()
488 rank = sdram_params->ch[channel].rank | 1; in data_training()
526 if (sdram_params->base.dramtype != LPDDR3) in data_training()
530 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
576 struct rk3288_sdram_params *sdram_params) in dram_cfg_rbc() argument
580 if (sdram_params->ch[chnum].bk == 3) in dram_cfg_rbc()
586 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
590 struct rk3288_sdram_params *sdram_params) in dram_all_config() argument
595 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
596 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; in dram_all_config()
597 for (chan = 0; chan < sdram_params->num_channels; chan++) { in dram_all_config()
599 &sdram_params->ch[chan]; in dram_all_config()
611 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
614 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
618 struct rk3288_sdram_params *sdram_params) in sdram_rank_bw_detect() argument
625 if (data_training(chan, channel, sdram_params) < 0) { in sdram_rank_bw_detect()
633 sdram_params->num_channels = 1; in sdram_rank_bw_detect()
638 sdram_params->ch[channel].rank = 1; in sdram_rank_bw_detect()
640 sdram_params->ch[channel].rank << 18); in sdram_rank_bw_detect()
645 sdram_params->ch[channel].bw = 1; in sdram_rank_bw_detect()
647 sdram_params->ch[channel].bw, in sdram_rank_bw_detect()
653 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
656 (data_training(chan, channel, sdram_params) < 0)) { in sdram_rank_bw_detect()
657 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
671 struct rk3288_sdram_params *sdram_params) in sdram_col_row_detect() argument
684 (1 << (col + sdram_params->ch[channel].bw - 1)); in sdram_col_row_detect()
695 sdram_params->ch[channel].col = col; in sdram_col_row_detect()
714 sdram_params->ch[channel].cs1_row = row; in sdram_col_row_detect()
715 sdram_params->ch[channel].row_3_4 = 0; in sdram_col_row_detect()
717 sdram_params->ch[channel].cs0_row = row; in sdram_col_row_detect()
724 static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params) in sdram_get_niu_config() argument
728 tmp = sdram_params->ch[0].col - 9; in sdram_get_niu_config()
729 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; in sdram_get_niu_config()
730 tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4); in sdram_get_niu_config()
739 sdram_params->base.ddrconfig = i; in sdram_get_niu_config()
745 static int sdram_get_stride(struct rk3288_sdram_params *sdram_params) in sdram_get_stride() argument
749 long cap = sdram_params->num_channels * (1u << in sdram_get_stride()
750 (sdram_params->ch[0].cs0_row + in sdram_get_stride()
751 sdram_params->ch[0].col + in sdram_get_stride()
752 (sdram_params->ch[0].rank - 1) + in sdram_get_stride()
753 sdram_params->ch[0].bw + in sdram_get_stride()
775 sdram_params->base.stride = stride; in sdram_get_stride()
781 struct rk3288_sdram_params *sdram_params) in sdram_init() argument
788 if ((sdram_params->base.dramtype == DDR3 && in sdram_init()
789 sdram_params->base.ddr_freq > 800000000) || in sdram_init()
790 (sdram_params->base.dramtype == LPDDR3 && in sdram_init()
791 sdram_params->base.ddr_freq > 533000000)) { in sdram_init()
797 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
815 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
817 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
819 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
821 phy_cfg(chan, channel, sdram_params); in sdram_init()
829 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
832 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
840 sdram_params->phy_timing.mr[1]); in sdram_init()
843 sdram_params->phy_timing.mr[2]); in sdram_init()
846 sdram_params->phy_timing.mr[3]); in sdram_init()
851 sdram_params->ch[channel].bw = 2; in sdram_init()
853 sdram_params->ch[channel].bw, dram->grf); in sdram_init()
860 sdram_params->ch[channel].rank = 2, in sdram_init()
862 (sdram_params->ch[channel].rank | 1) << 18); in sdram_init()
871 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
875 sdram_params->ch[channel].rank | 1, in sdram_init()
877 sdram_params->base.odt ? 3 : 0); in sdram_init()
890 sdram_rank_bw_detect(dram, channel, sdram_params); in sdram_init()
892 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
901 sdram_params->ch[channel].bk = 3; in sdram_init()
903 ret = sdram_col_row_detect(dram, channel, sdram_params); in sdram_init()
908 ret = sdram_get_niu_config(sdram_params); in sdram_init()
912 ret = sdram_get_stride(sdram_params); in sdram_init()
916 dram_all_config(dram, sdram_params); in sdram_init()