299 	u32 mode_sel;  in phy_io_config()  local
399 		mode_sel = 0x6;  in phy_io_config()
401 		mode_sel = 0x0;  in phy_io_config()
403 		mode_sel = 0x1;  in phy_io_config()
408 	clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);  in phy_io_config()
410 	clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);  in phy_io_config()
412 	clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);  in phy_io_config()
414 	clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);  in phy_io_config()
416 	clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);  in phy_io_config()
418 	clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);  in phy_io_config()
420 	clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);  in phy_io_config()
422 	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);  in phy_io_config()