Lines Matching refs:sdram_params
64 struct rk3399_sdram_params sdram_params;
112 const struct rk3399_sdram_params *sdram_params) in set_memory_map() argument
115 &sdram_params->ch[channel]; in set_memory_map()
151 if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) in set_memory_map()
156 const struct rk3399_sdram_params *sdram_params) in set_ds_odt() argument
166 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
176 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
198 if (sdram_params->base.odt == 1) in set_ds_odt()
295 const struct rk3399_sdram_params *sdram_params) in phy_io_config() argument
305 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
311 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
312 if (sdram_params->base.odt == 1) { in phy_io_config()
371 } else if (sdram_params->base.dramtype == DDR3) { in phy_io_config()
398 if (sdram_params->base.dramtype == LPDDR4) in phy_io_config()
400 else if (sdram_params->base.dramtype == LPDDR3) in phy_io_config()
402 else if (sdram_params->base.dramtype == DDR3) in phy_io_config()
426 if (sdram_params->base.ddr_freq < 400) in phy_io_config()
428 else if (sdram_params->base.ddr_freq < 800) in phy_io_config()
430 else if (sdram_params->base.ddr_freq < 1200) in phy_io_config()
456 const struct rk3399_sdram_params *sdram_params) in pctl_cfg() argument
461 const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; in pctl_cfg()
462 const u32 *params_phy = sdram_params->phy_regs.denali_phy; in pctl_cfg()
475 copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], in pctl_cfg()
478 set_memory_map(chan, channel, sdram_params); in pctl_cfg()
480 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); in pctl_cfg()
481 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); in pctl_cfg()
482 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); in pctl_cfg()
513 set_ds_odt(chan, sdram_params); in pctl_cfg()
541 ret = phy_io_config(chan, sdram_params); in pctl_cfg()
612 const struct rk3399_sdram_params *sdram_params) in data_training_ca() argument
618 u32 rank = sdram_params->ch[channel].rank; in data_training_ca()
662 const struct rk3399_sdram_params *sdram_params) in data_training_wl() argument
668 u32 rank = sdram_params->ch[channel].rank; in data_training_wl()
718 const struct rk3399_sdram_params *sdram_params) in data_training_rg() argument
724 u32 rank = sdram_params->ch[channel].rank; in data_training_rg()
775 const struct rk3399_sdram_params *sdram_params) in data_training_rl() argument
779 u32 rank = sdram_params->ch[channel].rank; in data_training_rl()
816 const struct rk3399_sdram_params *sdram_params) in data_training_wdql() argument
820 u32 rank = sdram_params->ch[channel].rank; in data_training_wdql()
856 const struct rk3399_sdram_params *sdram_params, in data_training() argument
865 if (sdram_params->base.dramtype == LPDDR4) { in data_training()
869 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
872 } else if (sdram_params->base.dramtype == DDR3) { in data_training()
881 data_training_ca(chan, channel, sdram_params); in data_training()
885 data_training_wl(chan, channel, sdram_params); in data_training()
889 data_training_rg(chan, channel, sdram_params); in data_training()
893 data_training_rl(chan, channel, sdram_params); in data_training()
897 data_training_wdql(chan, channel, sdram_params); in data_training()
906 const struct rk3399_sdram_params *sdram_params, in set_ddrconfig() argument
914 cs0_cap = (1 << (sdram_params->ch[channel].cs0_row in set_ddrconfig()
915 + sdram_params->ch[channel].col in set_ddrconfig()
916 + sdram_params->ch[channel].bk in set_ddrconfig()
917 + sdram_params->ch[channel].bw - 20)); in set_ddrconfig()
918 if (sdram_params->ch[channel].rank > 1) in set_ddrconfig()
919 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row in set_ddrconfig()
920 - sdram_params->ch[channel].cs1_row); in set_ddrconfig()
921 if (sdram_params->ch[channel].row_3_4) { in set_ddrconfig()
932 const struct rk3399_sdram_params *sdram_params) in dram_all_config() argument
937 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
938 sys_reg |= (sdram_params->base.num_channels - 1) in dram_all_config()
941 (idx < sdram_params->base.num_channels) && (channel < 2); in dram_all_config()
944 &sdram_params->ch[channel]; in dram_all_config()
948 if (sdram_params->ch[channel].col == 0) in dram_all_config()
962 noc_timing = &sdram_params->ch[channel].noc_timings; in dram_all_config()
975 if (sdram_params->ch[channel].rank == 1) in dram_all_config()
982 sdram_params->base.stride << 10); in dram_all_config()
992 const struct rk3399_sdram_params *sdram_params) in switch_to_phy_index1() argument
996 u32 ch_count = sdram_params->base.num_channels; in switch_to_phy_index1()
1027 sdram_params, PI_FULL_TRAINING); in switch_to_phy_index1()
1038 const struct rk3399_sdram_params *sdram_params) in sdram_init() argument
1040 unsigned char dramtype = sdram_params->base.dramtype; in sdram_init()
1041 unsigned int ddr_freq = sdram_params->base.ddr_freq; in sdram_init()
1059 if (channel >= sdram_params->base.num_channels) in sdram_init()
1062 if (pctl_cfg(chan, channel, sdram_params) != 0) { in sdram_init()
1072 sdram_params, PI_FULL_TRAINING)) { in sdram_init()
1077 set_ddrconfig(chan, sdram_params, channel, in sdram_init()
1078 sdram_params->ch[channel].ddrconfig); in sdram_init()
1080 dram_all_config(dram, sdram_params); in sdram_init()
1081 switch_to_phy_index1(dram, sdram_params); in sdram_init()
1094 (u32 *)&plat->sdram_params, in rk3399_dmc_ofdata_to_platdata()
1095 sizeof(plat->sdram_params) / sizeof(u32)); in rk3399_dmc_ofdata_to_platdata()
1132 struct rk3399_sdram_params *params = &plat->sdram_params; in rk3399_dmc_init()