Lines Matching refs:port
28 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ argument
41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 argument
49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ argument
57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ argument
75 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
81 # define SCSCR_INIT(port) 0x3B argument
87 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ argument
95 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
109 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ argument
123 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
137 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ argument
139 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ argument
140 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
142 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ argument
143 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
151 # define SCSCR_INIT(port) 0x38 argument
158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
164 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ argument
172 # define SCSCR_INIT(port) 0x38 argument
175 # define SCSCR_INIT(port) 0x3a argument
187 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
203 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
213 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
219 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
226 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ argument
234 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) argument
260 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
327 #define SCxSR_TEND(port)\ argument
328 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
329 #define SCxSR_ERRORS(port)\ argument
330 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
331 #define SCxSR_RDxF(port)\ argument
332 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
333 #define SCxSR_TDxE(port)\ argument
334 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
335 #define SCxSR_FER(port)\ argument
336 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
337 #define SCxSR_PER(port)\ argument
338 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
339 #define SCxSR_BRK(port)\ argument
340 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
341 #define SCxSR_ORER(port)\ argument
342 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
352 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) argument
353 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) argument
354 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) argument
355 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) argument
357 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) argument
358 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) argument
359 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) argument
360 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) argument
385 return readb(port->membase + (offset));\
387 return readw(port->membase + (offset));\
391 writeb(value, port->membase + (offset));\
393 writew(value, port->membase + (offset));\
397 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
398 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
404 static inline void sci_##name##_out(struct uart_port *port,\
406 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
416 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
419 static inline void sci_##name##_out(struct uart_port *port,\
424 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
427 static inline void sci_##name##_out(struct uart_port *port,\
434 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
437 static inline void sci_##name##_out(struct uart_port *port,\
624 #define sci_in(port, reg) sci_##reg##_in(port) argument
625 #define sci_out(port, reg, value) sci_##reg##_out(port, value) argument
630 int port; /* GPIO port no */ member
635 .port = H8300_GPIO_P9,
640 .port = H8300_GPIO_P9,
645 .port = H8300_GPIO_PB,
651 .port = H8300_GPIO_P3,
656 .port = H8300_GPIO_P3,
661 .port = H8300_GPIO_P5,
673 static inline int sci_rxd_in(struct uart_port *port) in sci_rxd_in() argument
675 if (port->mapbase == 0xfffffe80) in sci_rxd_in()
685 static inline int sci_rxd_in(struct uart_port *port) in sci_rxd_in() argument
687 if (port->mapbase == 0xffe00000) in sci_rxd_in()
692 static inline int sci_rxd_in(struct uart_port *port) in sci_rxd_in() argument
694 int ch = (port->mapbase - SMR0) >> 3; in sci_rxd_in()
698 static inline int sci_rxd_in(struct uart_port *port) in sci_rxd_in() argument
752 static inline int scbrr_calc(struct uart_port *port, int bps, int clk) in scbrr_calc() argument
754 if (port->type == PORT_SCIF) in scbrr_calc()
759 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)