377 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)  in cadence_qspi_apb_controller_init()  argument
381 	cadence_qspi_apb_controller_disable(plat->regbase);  in cadence_qspi_apb_controller_init()
384 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
388 	reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);  in cadence_qspi_apb_controller_init()
389 	reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);  in cadence_qspi_apb_controller_init()
390 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
393 	writel(0, plat->regbase + CQSPI_REG_REMAP);  in cadence_qspi_apb_controller_init()
396 	writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);  in cadence_qspi_apb_controller_init()
399 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);  in cadence_qspi_apb_controller_init()
401 	cadence_qspi_apb_controller_enable(plat->regbase);  in cadence_qspi_apb_controller_init()
531 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_read_setup()  argument
556 	writel(plat->trigger_address,  in cadence_qspi_apb_indirect_read_setup()
557 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_read_setup()
568 	writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);  in cadence_qspi_apb_indirect_read_setup()
578 		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
580 		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
593 	writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_indirect_read_setup()
596 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
599 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
603 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)  in cadence_qspi_get_rd_sram_level()  argument
605 	u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);  in cadence_qspi_get_rd_sram_level()
610 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)  in cadence_qspi_wait_for_data()  argument
616 		reg = cadence_qspi_get_rd_sram_level(plat);  in cadence_qspi_wait_for_data()
625 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_read_execute()  argument
632 	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);  in cadence_qspi_apb_indirect_read_execute()
636 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
639 		ret = cadence_qspi_wait_for_data(plat);  in cadence_qspi_apb_indirect_read_execute()
648 			bytes_to_read *= plat->fifo_width;  in cadence_qspi_apb_indirect_read_execute()
656 				readsb(plat->ahbbase, rxbuf, bytes_to_read);  in cadence_qspi_apb_indirect_read_execute()
658 				readsl(plat->ahbbase, rxbuf,  in cadence_qspi_apb_indirect_read_execute()
662 			bytes_to_read = cadence_qspi_get_rd_sram_level(plat);  in cadence_qspi_apb_indirect_read_execute()
667 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,  in cadence_qspi_apb_indirect_read_execute()
676 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
683 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
688 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_write_setup()  argument
700 	writel(plat->trigger_address,  in cadence_qspi_apb_indirect_write_setup()
701 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_write_setup()
705 	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);  in cadence_qspi_apb_indirect_write_setup()
709 	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);  in cadence_qspi_apb_indirect_write_setup()
711 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
714 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
718 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_write_execute()  argument
721 	unsigned int page_size = plat->page_size;  in cadence_qspi_apb_indirect_write_execute()
741 	writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);  in cadence_qspi_apb_indirect_write_execute()
745 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
749 		writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);  in cadence_qspi_apb_indirect_write_execute()
751 			writesb(plat->ahbbase,  in cadence_qspi_apb_indirect_write_execute()
755 		ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,  in cadence_qspi_apb_indirect_write_execute()
768 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,  in cadence_qspi_apb_indirect_write_execute()
777 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
785 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()