142 	struct fsl_qspi_priv priv;  member
158 static inline int is_controller_busy(const struct fsl_qspi_priv *priv)  in is_controller_busy()  argument
166 		val = qspi_read32(priv->flags, &priv->regs->sr);  in is_controller_busy()
188 static void qspi_set_lut(struct fsl_qspi_priv *priv)  in qspi_set_lut()  argument
190 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_set_lut()
194 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);  in qspi_set_lut()
195 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);  in qspi_set_lut()
199 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |  in qspi_set_lut()
201 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
202 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
203 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
208 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
214 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
219 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
225 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
229 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
230 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
234 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |  in qspi_set_lut()
237 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
238 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
239 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
244 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |  in qspi_set_lut()
249 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
254 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
259 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
260 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
261 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
265 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
268 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
269 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
270 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
275 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |  in qspi_set_lut()
280 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
285 		qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
296 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |  in qspi_set_lut()
299 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
303 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
304 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
308 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |  in qspi_set_lut()
311 	qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);  in qspi_set_lut()
312 	qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);  in qspi_set_lut()
313 	qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);  in qspi_set_lut()
317 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |  in qspi_set_lut()
328 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |  in qspi_set_lut()
333 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |  in qspi_set_lut()
338 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |  in qspi_set_lut()
343 	qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |  in qspi_set_lut()
353 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
357 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
367 	qspi_write32(priv->flags, &regs->lut[lut_base],  in qspi_set_lut()
371 	qspi_write32(priv->flags, &regs->lut[lut_base + 1],  in qspi_set_lut()
375 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);  in qspi_set_lut()
376 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);  in qspi_set_lut()
386 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)  in qspi_ahb_invalid()  argument
388 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_ahb_invalid()
391 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_invalid()
393 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_ahb_invalid()
402 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_ahb_invalid()
406 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)  in qspi_ahb_read()  argument
408 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_ahb_read()
412 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_read()
414 	qspi_write32(priv->flags, &regs->mcr,  in qspi_ahb_read()
418 	rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);  in qspi_ahb_read()
422 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_ahb_read()
425 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)  in qspi_enable_ddr_mode()  argument
428 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_enable_ddr_mode()
430 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_enable_ddr_mode()
432 	qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);  in qspi_enable_ddr_mode()
435 	reg2 = qspi_read32(priv->flags, &regs->smpr);  in qspi_enable_ddr_mode()
438 	qspi_write32(priv->flags, &regs->smpr, reg2);  in qspi_enable_ddr_mode()
445 	qspi_write32(priv->flags, &regs->mcr, reg);  in qspi_enable_ddr_mode()
461 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)  in qspi_init_ahb_read()  argument
463 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_init_ahb_read()
466 	qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
467 	qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
468 	qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);  in qspi_init_ahb_read()
469 	qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |  in qspi_init_ahb_read()
473 	qspi_write32(priv->flags, &regs->buf0ind, 0);  in qspi_init_ahb_read()
474 	qspi_write32(priv->flags, &regs->buf1ind, 0);  in qspi_init_ahb_read()
475 	qspi_write32(priv->flags, &regs->buf2ind, 0);  in qspi_init_ahb_read()
481 	qspi_write32(priv->flags, &regs->bfgencr,  in qspi_init_ahb_read()
485 	qspi_enable_ddr_mode(priv);  in qspi_init_ahb_read()
491 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)  in qspi_op_rdbank()  argument
493 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdbank()
496 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdbank()
497 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdbank()
500 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdbank()
502 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdbank()
504 	if (priv->cur_seqid == QSPI_CMD_BRRD)  in qspi_op_rdbank()
509 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdbank()
513 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdbank()
519 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdbank()
521 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdbank()
524 			qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdbank()
525 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdbank()
531 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdbank()
535 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)  in qspi_op_rdid()  argument
537 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdid()
541 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdid()
542 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdid()
545 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdid()
547 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdid()
549 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdid()
551 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdid()
558 		rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdid()
560 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_rdid()
570 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdid()
574 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)  in qspi_op_read()  argument
576 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_read()
582 	if (priv->cur_seqid == QSPI_CMD_RDAR)  in qspi_op_read()
587 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_read()
588 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_read()
591 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_read()
593 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_read()
598 		qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_read()
603 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_read()
606 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_read()
614 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_read()
624 		qspi_write32(priv->flags, &regs->mcr,  in qspi_op_read()
625 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_read()
629 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_read()
632 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)  in qspi_op_write()  argument
634 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_write()
639 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_write()
640 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_write()
643 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_write()
649 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
651 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
654 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
656 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
659 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_write()
661 			status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_write()
664 		qspi_write32(priv->flags, &regs->mcr,  in qspi_op_write()
665 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_write()
671 	if (priv->cur_seqid == QSPI_CMD_WRAR)  in qspi_op_write()
674 	if (priv->cur_seqid == QSPI_CMD_BRWR)  in qspi_op_write()
676 	else if (priv->cur_seqid == QSPI_CMD_WREAR)  in qspi_op_write()
680 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_write()
682 	qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_write()
697 		qspi_write32(priv->flags, &regs->tbdr, data);  in qspi_op_write()
701 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_write()
703 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
706 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_write()
709 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)  in qspi_op_rdsr()  argument
711 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_rdsr()
714 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdsr()
715 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdsr()
718 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_rdsr()
720 	qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);  in qspi_op_rdsr()
722 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_rdsr()
724 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdsr()
730 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdsr()
732 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdsr()
735 			qspi_write32(priv->flags, &regs->mcr,  in qspi_op_rdsr()
736 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdsr()
742 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_rdsr()
745 static void qspi_op_erase(struct fsl_qspi_priv *priv)  in qspi_op_erase()  argument
747 	struct fsl_qspi_regs *regs = priv->regs;  in qspi_op_erase()
751 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_erase()
752 	qspi_write32(priv->flags, &regs->mcr,  in qspi_op_erase()
755 	qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);  in qspi_op_erase()
757 	to_or_from = priv->sf_addr + priv->cur_amba_base;  in qspi_op_erase()
758 	qspi_write32(priv->flags, &regs->sfar, to_or_from);  in qspi_op_erase()
760 	qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
762 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
765 	if (priv->cur_seqid == QSPI_CMD_SE) {  in qspi_op_erase()
766 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
768 	} else if (priv->cur_seqid == QSPI_CMD_BE_4K) {  in qspi_op_erase()
769 		qspi_write32(priv->flags, &regs->ipcr,  in qspi_op_erase()
772 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
775 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);  in qspi_op_erase()
778 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,  in qspi_xfer()  argument
789 			priv->cur_seqid = *(u8 *)dout;  in qspi_xfer()
794 			priv->sf_addr = wr_sfaddr;  in qspi_xfer()
795 			qspi_op_write(priv, (u8 *)dout, bytes);  in qspi_xfer()
799 		if (priv->cur_seqid == QSPI_CMD_FAST_READ ||  in qspi_xfer()
800 		    priv->cur_seqid == QSPI_CMD_RDAR) {  in qspi_xfer()
801 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;  in qspi_xfer()
802 		} else if ((priv->cur_seqid == QSPI_CMD_SE) ||  in qspi_xfer()
803 			   (priv->cur_seqid == QSPI_CMD_BE_4K)) {  in qspi_xfer()
804 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;  in qspi_xfer()
805 			qspi_op_erase(priv);  in qspi_xfer()
806 		} else if (priv->cur_seqid == QSPI_CMD_PP ||  in qspi_xfer()
807 			   priv->cur_seqid == QSPI_CMD_WRAR) {  in qspi_xfer()
809 		} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||  in qspi_xfer()
810 			 (priv->cur_seqid == QSPI_CMD_WREAR)) {  in qspi_xfer()
818 		if (priv->cur_seqid == QSPI_CMD_FAST_READ) {  in qspi_xfer()
820 			qspi_ahb_read(priv, din, bytes);  in qspi_xfer()
822 			qspi_op_read(priv, din, bytes);  in qspi_xfer()
824 		} else if (priv->cur_seqid == QSPI_CMD_RDAR) {  in qspi_xfer()
825 			qspi_op_read(priv, din, bytes);  in qspi_xfer()
826 		} else if (priv->cur_seqid == QSPI_CMD_RDID)  in qspi_xfer()
827 			qspi_op_rdid(priv, din, bytes);  in qspi_xfer()
828 		else if (priv->cur_seqid == QSPI_CMD_RDSR)  in qspi_xfer()
829 			qspi_op_rdsr(priv, din, bytes);  in qspi_xfer()
831 		else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||  in qspi_xfer()
832 			 (priv->cur_seqid == QSPI_CMD_RDEAR)) {  in qspi_xfer()
833 			priv->sf_addr = 0;  in qspi_xfer()
834 			qspi_op_rdbank(priv, din, bytes);  in qspi_xfer()
840 	if ((priv->cur_seqid == QSPI_CMD_SE) ||  in qspi_xfer()
841 	    (priv->cur_seqid == QSPI_CMD_PP) ||  in qspi_xfer()
842 	    (priv->cur_seqid == QSPI_CMD_BE_4K) ||  in qspi_xfer()
843 	    (priv->cur_seqid == QSPI_CMD_WREAR) ||  in qspi_xfer()
844 	    (priv->cur_seqid == QSPI_CMD_BRWR))  in qspi_xfer()
845 		qspi_ahb_invalid(priv);  in qspi_xfer()
851 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)  in qspi_module_disable()  argument
855 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in qspi_module_disable()
860 	qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);  in qspi_module_disable()
863 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)  in qspi_cfg_smpr()  argument
867 	smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);  in qspi_cfg_smpr()
870 	qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);  in qspi_cfg_smpr()
911 	qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;  in spi_setup_slave()
915 	qspi->priv.regs = regs;  in spi_setup_slave()
923 	qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;  in spi_setup_slave()
927 	mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);  in spi_setup_slave()
933 	qspi_write32(qspi->priv.flags, &regs->mcr,  in spi_setup_slave()
937 	qspi_cfg_smpr(&qspi->priv,  in spi_setup_slave()
952 	qspi_write32(qspi->priv.flags, &regs->sfa1ad,  in spi_setup_slave()
954 	qspi_write32(qspi->priv.flags, &regs->sfa2ad,  in spi_setup_slave()
956 	qspi_write32(qspi->priv.flags, &regs->sfb1ad,  in spi_setup_slave()
958 	qspi_write32(qspi->priv.flags, &regs->sfb2ad,  in spi_setup_slave()
961 	qspi_set_lut(&qspi->priv);  in spi_setup_slave()
964 	qspi_init_ahb_read(&qspi->priv);  in spi_setup_slave()
967 	qspi_module_disable(&qspi->priv, 0);  in spi_setup_slave()
994 	return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);  in spi_xfer()
1016 	struct fsl_qspi_priv *priv = dev_get_priv(bus);  in fsl_qspi_probe()  local
1024 	priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;  in fsl_qspi_probe()
1025 	priv->flags = plat->flags;  in fsl_qspi_probe()
1027 	priv->speed_hz = plat->speed_hz;  in fsl_qspi_probe()
1033 	priv->amba_base[0] = (u32)plat->amba_base;  in fsl_qspi_probe()
1034 	priv->amba_total_size = (u32)plat->amba_total_size;  in fsl_qspi_probe()
1035 	priv->flash_num = plat->flash_num;  in fsl_qspi_probe()
1036 	priv->num_chipselect = plat->num_chipselect;  in fsl_qspi_probe()
1039 	ret = is_controller_busy(priv);  in fsl_qspi_probe()
1046 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in fsl_qspi_probe()
1052 	qspi_write32(priv->flags, &priv->regs->mcr,  in fsl_qspi_probe()
1056 	qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |  in fsl_qspi_probe()
1069 	amba_size_per_chip = priv->amba_total_size >>  in fsl_qspi_probe()
1070 			     (priv->num_chipselect >> 1);  in fsl_qspi_probe()
1071 	for (i = 1 ; i < priv->num_chipselect ; i++)  in fsl_qspi_probe()
1072 		priv->amba_base[i] =  in fsl_qspi_probe()
1073 			amba_size_per_chip + priv->amba_base[i - 1];  in fsl_qspi_probe()
1085 	qspi_write32(priv->flags, &priv->regs->sfa1ad,  in fsl_qspi_probe()
1086 		     priv->amba_base[0] + amba_size_per_chip);  in fsl_qspi_probe()
1087 	switch (priv->num_chipselect) {  in fsl_qspi_probe()
1091 		qspi_write32(priv->flags, &priv->regs->sfa2ad,  in fsl_qspi_probe()
1092 			     priv->amba_base[1]);  in fsl_qspi_probe()
1093 		qspi_write32(priv->flags, &priv->regs->sfb1ad,  in fsl_qspi_probe()
1094 			     priv->amba_base[1] + amba_size_per_chip);  in fsl_qspi_probe()
1095 		qspi_write32(priv->flags, &priv->regs->sfb2ad,  in fsl_qspi_probe()
1096 			     priv->amba_base[1] + amba_size_per_chip);  in fsl_qspi_probe()
1099 		qspi_write32(priv->flags, &priv->regs->sfa2ad,  in fsl_qspi_probe()
1100 			     priv->amba_base[2]);  in fsl_qspi_probe()
1101 		qspi_write32(priv->flags, &priv->regs->sfb1ad,  in fsl_qspi_probe()
1102 			     priv->amba_base[3]);  in fsl_qspi_probe()
1103 		qspi_write32(priv->flags, &priv->regs->sfb2ad,  in fsl_qspi_probe()
1104 			     priv->amba_base[3] + amba_size_per_chip);  in fsl_qspi_probe()
1108 		      priv->num_chipselect);  in fsl_qspi_probe()
1109 		qspi_module_disable(priv, 1);  in fsl_qspi_probe()
1113 	qspi_set_lut(priv);  in fsl_qspi_probe()
1116 	qspi_init_ahb_read(priv);  in fsl_qspi_probe()
1119 	qspi_module_disable(priv, 0);  in fsl_qspi_probe()
1182 	struct fsl_qspi_priv *priv;  in fsl_qspi_xfer()  local
1186 	priv = dev_get_priv(bus);  in fsl_qspi_xfer()
1188 	return qspi_xfer(priv, bitlen, dout, din, flags);  in fsl_qspi_xfer()
1193 	struct fsl_qspi_priv *priv;  in fsl_qspi_claim_bus()  local
1199 	priv = dev_get_priv(bus);  in fsl_qspi_claim_bus()
1202 	ret = is_controller_busy(priv);  in fsl_qspi_claim_bus()
1209 	priv->cur_amba_base = priv->amba_base[slave_plat->cs];  in fsl_qspi_claim_bus()
1211 	qspi_module_disable(priv, 0);  in fsl_qspi_claim_bus()
1218 	struct fsl_qspi_priv *priv;  in fsl_qspi_release_bus()  local
1222 	priv = dev_get_priv(bus);  in fsl_qspi_release_bus()
1224 	qspi_module_disable(priv, 1);  in fsl_qspi_release_bus()