146 static u32 qspi_read32(u32 flags, u32 *addr)  in qspi_read32()  function
166 		val = qspi_read32(priv->flags, &priv->regs->sr);  in is_controller_busy()
391 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_invalid()
412 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_read()
430 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_enable_ddr_mode()
435 	reg2 = qspi_read32(priv->flags, &regs->smpr);  in qspi_enable_ddr_mode()
496 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdbank()
513 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdbank()
519 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdbank()
521 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdbank()
525 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdbank()
541 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdid()
551 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdid()
558 		rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdid()
560 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_rdid()
587 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_read()
606 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_read()
614 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_read()
625 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_read()
639 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_write()
651 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
656 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
659 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_write()
661 			status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_write()
665 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_write()
703 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
714 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdsr()
724 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdsr()
730 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdsr()
732 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdsr()
736 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdsr()
751 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_erase()
762 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
772 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
855 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in qspi_module_disable()
867 	smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);  in qspi_cfg_smpr()
927 	mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);  in spi_setup_slave()
1046 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in fsl_qspi_probe()