Lines Matching refs:musb
82 static void musb_ep_program(struct musb *musb, u8 epnum,
91 struct musb *musb = ep->musb; in musb_h_tx_flush_fifo() local
100 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); in musb_h_tx_flush_fifo()
188 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) in musb_start_urb() argument
192 void __iomem *mbase = musb->mregs; in musb_start_urb()
210 musb->ep0_stage = MUSB_EP0_START; in musb_start_urb()
228 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", in musb_start_urb()
243 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); in musb_start_urb()
255 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); in musb_start_urb()
272 dev_dbg(musb->controller, "SOF for %d\n", epnum); in musb_start_urb()
282 dev_dbg(musb->controller, "Start TX%d %s\n", epnum, in musb_start_urb()
293 static void musb_giveback(struct musb *musb, struct urb *urb, int status) in musb_giveback() argument
294 __releases(musb->lock) in musb_giveback()
295 __acquires(musb->lock) in musb_giveback()
297 dev_dbg(musb->controller, in musb_giveback()
306 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); in musb_giveback()
307 spin_unlock(&musb->lock); in musb_giveback()
308 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); in musb_giveback()
309 spin_lock(&musb->lock); in musb_giveback()
339 static void musb_advance_schedule(struct musb *musb, struct urb *urb, in musb_advance_schedule() argument
364 musb_giveback(musb, urb, status); in musb_advance_schedule()
372 struct dma_controller *dma = musb->dma_controller; in musb_advance_schedule()
420 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", in musb_advance_schedule()
422 musb_start_urb(musb, is_in, qh); in musb_advance_schedule()
449 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) in musb_host_packet_rx() argument
457 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_packet_rx()
465 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, in musb_host_packet_rx()
488 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); in musb_host_packet_rx()
507 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); in musb_host_packet_rx()
554 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) in musb_rx_reinit() argument
592 if (musb->is_multipoint) { in musb_rx_reinit()
598 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); in musb_rx_reinit()
607 if (musb->double_buffer_not_ok) in musb_rx_reinit()
682 static void musb_ep_program(struct musb *musb, u8 epnum, in musb_ep_program() argument
689 void __iomem *mbase = musb->mregs; in musb_ep_program()
690 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_ep_program()
695 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " in musb_ep_program()
706 dma_controller = musb->dma_controller; in musb_ep_program()
771 if (musb->is_multipoint) { in musb_ep_program()
782 if (musb->double_buffer_not_ok) in musb_ep_program()
785 else if (can_bulk_split(musb, qh->type)) in musb_ep_program()
796 if (musb->is_multipoint) in musb_ep_program()
801 if (can_bulk_split(musb, qh->type)) in musb_ep_program()
825 musb_rx_reinit(musb, qh, hw_ep); in musb_ep_program()
877 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); in musb_ep_program()
888 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) in musb_h_ep0_continue() argument
893 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_continue()
897 switch (musb->ep0_stage) { in musb_h_ep0_continue()
920 dev_dbg(musb->controller, "start no-DATA\n"); in musb_h_ep0_continue()
923 dev_dbg(musb->controller, "start IN-DATA\n"); in musb_h_ep0_continue()
924 musb->ep0_stage = MUSB_EP0_IN; in musb_h_ep0_continue()
928 dev_dbg(musb->controller, "start OUT-DATA\n"); in musb_h_ep0_continue()
929 musb->ep0_stage = MUSB_EP0_OUT; in musb_h_ep0_continue()
940 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", in musb_h_ep0_continue()
951 ERR("bogus ep0 stage %d\n", musb->ep0_stage); in musb_h_ep0_continue()
964 irqreturn_t musb_h_ep0_irq(struct musb *musb) in musb_h_ep0_irq() argument
969 void __iomem *mbase = musb->mregs; in musb_h_ep0_irq()
970 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_irq()
985 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", in musb_h_ep0_irq()
986 csr, qh, len, urb, musb->ep0_stage); in musb_h_ep0_irq()
989 if (MUSB_EP0_STATUS == musb->ep0_stage) { in musb_h_ep0_irq()
996 dev_dbg(musb->controller, "STALLING ENDPOINT\n"); in musb_h_ep0_irq()
1000 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); in musb_h_ep0_irq()
1004 dev_dbg(musb->controller, "control NAK timeout\n"); in musb_h_ep0_irq()
1019 dev_dbg(musb->controller, "aborting\n"); in musb_h_ep0_irq()
1052 if (musb_h_ep0_continue(musb, len, urb)) { in musb_h_ep0_irq()
1054 csr = (MUSB_EP0_IN == musb->ep0_stage) in musb_h_ep0_irq()
1067 musb->ep0_stage = MUSB_EP0_STATUS; in musb_h_ep0_irq()
1069 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); in musb_h_ep0_irq()
1075 musb->ep0_stage = MUSB_EP0_IDLE; in musb_h_ep0_irq()
1079 musb_advance_schedule(musb, urb, hw_ep, 1); in musb_h_ep0_irq()
1102 void musb_host_tx(struct musb *musb, u8 epnum) in musb_host_tx() argument
1109 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_tx()
1114 void __iomem *mbase = musb->mregs; in musb_host_tx()
1123 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); in musb_host_tx()
1129 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, in musb_host_tx()
1135 dev_dbg(musb->controller, "TX end %d stall\n", epnum); in musb_host_tx()
1142 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); in musb_host_tx()
1147 dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum); in musb_host_tx()
1167 (void) musb->dma_controller->channel_abort(dma); in musb_host_tx()
1192 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); in musb_host_tx()
1251 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " in musb_host_tx()
1310 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); in musb_host_tx()
1313 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, in musb_host_tx()
1320 dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); in musb_host_tx()
1334 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); in musb_host_tx()
1386 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) in musb_bulk_rx_nak_timeout() argument
1390 void __iomem *mbase = musb->mregs; in musb_bulk_rx_nak_timeout()
1404 cur_qh = first_qh(&musb->in_bulk); in musb_bulk_rx_nak_timeout()
1409 musb->dma_controller->channel_abort(dma); in musb_bulk_rx_nak_timeout()
1416 list_move_tail(&cur_qh->ring, &musb->in_bulk); in musb_bulk_rx_nak_timeout()
1419 next_qh = first_qh(&musb->in_bulk); in musb_bulk_rx_nak_timeout()
1423 musb_start_urb(musb, 1, next_qh); in musb_bulk_rx_nak_timeout()
1431 void musb_host_rx(struct musb *musb, u8 epnum) in musb_host_rx() argument
1434 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_rx()
1438 void __iomem *mbase = musb->mregs; in musb_host_rx()
1461 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, in musb_host_rx()
1469 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", in musb_host_rx()
1476 dev_dbg(musb->controller, "RX end %d STALL\n", epnum); in musb_host_rx()
1482 dev_dbg(musb->controller, "end %d RX proto error\n", epnum); in musb_host_rx()
1490 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); in musb_host_rx()
1502 && !list_is_singular(&musb->in_bulk)) { in musb_host_rx()
1503 musb_bulk_rx_nak_timeout(musb, hw_ep); in musb_host_rx()
1513 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); in musb_host_rx()
1518 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", in musb_host_rx()
1528 (void) musb->dma_controller->channel_abort(dma); in musb_host_rx()
1559 (void) musb->dma_controller->channel_abort(dma); in musb_host_rx()
1564 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, in musb_host_rx()
1614 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, in musb_host_rx()
1647 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n", in musb_host_rx()
1654 c = musb->dma_controller; in musb_host_rx()
1671 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\ in musb_host_rx()
1760 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); in musb_host_rx()
1761 done = musb_host_packet_rx(musb, urb, in musb_host_rx()
1763 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); in musb_host_rx()
1773 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); in musb_host_rx()
1783 struct musb *musb, in musb_schedule() argument
1798 head = &musb->control; in musb_schedule()
1799 hw_ep = musb->control_ep; in musb_schedule()
1815 for (epnum = 1, hw_ep = musb->endpoints + 1; in musb_schedule()
1816 epnum < musb->nr_endpoints; in musb_schedule()
1823 if (hw_ep == musb->bulk_ep) in musb_schedule()
1846 hw_ep = musb->endpoints + epnum; in musb_schedule()
1860 hw_ep = musb->bulk_ep; in musb_schedule()
1862 head = &musb->in_bulk; in musb_schedule()
1864 head = &musb->out_bulk; in musb_schedule()
1883 hw_ep = musb->endpoints + best_end; in musb_schedule()
1884 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); in musb_schedule()
1894 musb_start_urb(musb, is_in, qh); in musb_schedule()
1900 static int tt_needed(struct musb *musb, struct usb_device *dev) in tt_needed() argument
1902 if ((musb_readb(musb->mregs, MUSB_POWER) & MUSB_POWER_HSMODE) && in tt_needed()
1919 struct musb *musb = hcd_to_musb(hcd); local
1928 if (!is_host_active(musb) || !musb->is_active)
1931 spin_lock_irqsave(&musb->lock, flags);
1936 spin_unlock_irqrestore(&musb->lock, flags);
1957 spin_lock_irqsave(&musb->lock, flags);
1959 spin_unlock_irqrestore(&musb->lock, flags);
1980 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1981 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2044 if (musb->is_multipoint) {
2069 if (tt_needed(musb, urb->dev)) {
2086 spin_lock_irqsave(&musb->lock, flags);
2095 ret = musb_schedule(musb, qh,
2104 spin_unlock_irqrestore(&musb->lock, flags);
2108 spin_lock_irqsave(&musb->lock, flags);
2110 spin_unlock_irqrestore(&musb->lock, flags);
2124 struct musb *musb = ep->musb; local
2127 void __iomem *regs = ep->musb->mregs;
2139 status = ep->musb->dma_controller->channel_abort(dma);
2140 dev_dbg(musb->controller,
2175 musb_advance_schedule(ep->musb, urb, ep, is_in);
2188 struct musb *musb = hcd_to_musb(hcd); local
2194 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2199 spin_lock_irqsave(&musb->lock, flags);
2226 musb_giveback(musb, urb, 0);
2240 spin_unlock_irqrestore(&musb->lock, flags);
2251 struct musb *musb = hcd_to_musb(hcd); local
2255 spin_lock_irqsave(&musb->lock, flags);
2281 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2289 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2296 spin_unlock_irqrestore(&musb->lock, flags);
2301 struct musb *musb = hcd_to_musb(hcd); local
2303 return musb_readw(musb->mregs, MUSB_FRAME);
2308 struct musb *musb = hcd_to_musb(hcd); local
2314 musb->port1_status = 0;
2326 struct musb *musb = hcd_to_musb(hcd); local
2329 if (!is_host_active(musb))
2332 switch (musb->xceiv->state) {
2340 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2342 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2348 if (musb->is_active) {
2350 otg_state_string(musb->xceiv->state));
2365 .hcd_priv_size = sizeof(struct musb),