324 static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,  in gtt_write()  function
363 	gtt_write(priv, PCH_PORT_HOTPLUG, reg32);  in igd_setup_panel()
369 	gtt_write(priv, PCH_PP_ON_DELAYS, reg32);  in igd_setup_panel()
374 	gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);  in igd_setup_panel()
381 		gtt_write(priv, PCH_PP_DIVISOR, reg32);  in igd_setup_panel()
386 		gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);  in igd_setup_panel()
387 		gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);  in igd_setup_panel()
390 		gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);  in igd_setup_panel()
391 		gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);  in igd_setup_panel()
452 			gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */  in igd_cdclk_init_haswell()
454 			gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */  in igd_cdclk_init_haswell()
455 		gtt_write(priv, 0x13812c, 0x00000000);  in igd_cdclk_init_haswell()
456 		gtt_write(priv, 0x138124, 0x80000017);  in igd_cdclk_init_haswell()
478 	gtt_write(priv, 0x138128, 0);  in igd_cdclk_init_broadwell()
479 	gtt_write(priv, 0x13812c, 0);  in igd_cdclk_init_broadwell()
480 	gtt_write(priv, 0x138124, 0x80000018);  in igd_cdclk_init_broadwell()
537 	gtt_write(priv, 0x138128, pwctl);  in igd_cdclk_init_broadwell()
538 	gtt_write(priv, 0x13812c, 0);  in igd_cdclk_init_broadwell()
539 	gtt_write(priv, 0x138124, 0x80000017);  in igd_cdclk_init_broadwell()
582 			gtt_write(priv, 0xa000, 0x300ff);  in igd_pre_init()
584 			gtt_write(priv, 0xa000, 0x30020);  in igd_pre_init()
594 	gtt_write(priv, 0xa008, rp1_gfx_freq << 24);  in igd_pre_init()