Lines Matching refs:da8xx_fb_reg_base
145 static struct da8xx_lcd_regs *da8xx_fb_reg_base; variable
224 &da8xx_fb_reg_base->clk_reset); in lcd_enable_raster()
230 &da8xx_fb_reg_base->clk_reset); in lcd_enable_raster()
234 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_enable_raster()
237 &da8xx_fb_reg_base->raster_ctrl); in lcd_enable_raster()
251 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_disable_raster()
254 &da8xx_fb_reg_base->raster_ctrl); in lcd_disable_raster()
259 stat = lcdc_read(&da8xx_fb_reg_base->stat); in lcd_disable_raster()
261 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat); in lcd_disable_raster()
267 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcd_disable_raster()
269 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); in lcd_disable_raster()
286 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_blit()
289 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); in lcd_blit()
299 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_blit()
303 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
308 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
309 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
310 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
311 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
314 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
315 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
316 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
317 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
328 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_blit()
330 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
333 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
334 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
337 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); in lcd_blit()
338 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcd_blit()
352 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; in lcd_cfg_dma()
372 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); in lcd_cfg_dma()
382 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; in lcd_cfg_ac_bias()
385 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_ac_bias()
393 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf; in lcd_cfg_horizontal_sync()
397 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_horizontal_sync()
405 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff; in lcd_cfg_vertical_sync()
409 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_vertical_sync()
417 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | in lcd_cfg_display()
446 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_cfg_display()
448 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_cfg_display()
451 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_display()
453 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_display()
475 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_display()
500 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_frame_buffer()
508 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_frame_buffer()
512 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_frame_buffer()
514 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_frame_buffer()
518 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_frame_buffer()
520 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_frame_buffer()
524 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); in lcd_cfg_frame_buffer()
534 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_frame_buffer()
633 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); in lcd_reset()
634 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); in lcd_reset()
637 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); in lcd_reset()
639 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
640 lcdc_write(0, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
657 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); in lcd_calc_clk_divider()
662 &da8xx_fb_reg_base->clk_ena); in lcd_calc_clk_divider()
677 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | in lcd_init()
679 &da8xx_fb_reg_base->raster_timing_2); in lcd_init()
681 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & in lcd_init()
683 &da8xx_fb_reg_base->raster_timing_2); in lcd_init()
720 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | in lcd_init()
721 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl); in lcd_init()
730 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_dma_start()
732 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_dma_start()
734 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcdc_dma_start()
736 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcdc_dma_start()
742 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
748 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
761 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
764 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcdc_irq_handler_rev01()
766 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcdc_irq_handler_rev01()
772 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
778 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_irq_handler_rev01()
780 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_irq_handler_rev01()
790 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
796 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
798 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
810 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
813 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | in lcdc_irq_handler_rev02()
815 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); in lcdc_irq_handler_rev02()
819 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
822 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
828 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_irq_handler_rev02()
830 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_irq_handler_rev02()
832 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
835 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
902 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE; in video_hw_init()
905 rev = lcdc_read(&da8xx_fb_reg_base->revid); in video_hw_init()
1011 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); in video_hw_init()
1013 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); in video_hw_init()