Lines Matching refs:hdmi
55 static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset) in hdmi_write() argument
57 switch (hdmi->reg_io_width) { in hdmi_write()
59 writeb(val, hdmi->ioaddr + offset); in hdmi_write()
62 writel(val, hdmi->ioaddr + (offset << 2)); in hdmi_write()
70 static u8 hdmi_read(struct dw_hdmi *hdmi, int offset) in hdmi_read() argument
72 switch (hdmi->reg_io_width) { in hdmi_read()
74 return readb(hdmi->ioaddr + offset); in hdmi_read()
76 return readl(hdmi->ioaddr + (offset << 2)); in hdmi_read()
85 static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data) in hdmi_mod() argument
87 u8 val = hdmi_read(hdmi, reg) & ~mask; in hdmi_mod()
90 hdmi_write(hdmi, val, reg); in hdmi_mod()
93 static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts) in hdmi_set_clock_regenerator() argument
100 hdmi_write(hdmi, n3, HDMI_AUD_N3); in hdmi_set_clock_regenerator()
109 hdmi_write(hdmi, cts3, HDMI_AUD_CTS3); in hdmi_set_clock_regenerator()
110 hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); in hdmi_set_clock_regenerator()
111 hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1); in hdmi_set_clock_regenerator()
115 hdmi_write(hdmi, n3, HDMI_AUD_N3); in hdmi_set_clock_regenerator()
116 hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); in hdmi_set_clock_regenerator()
117 hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3); in hdmi_set_clock_regenerator()
119 hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS); in hdmi_set_clock_regenerator()
136 static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk) in hdmi_audio_set_samplerate() argument
149 hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts); in hdmi_audio_set_samplerate()
159 static void hdmi_video_sample(struct dw_hdmi *hdmi) in hdmi_video_sample() argument
168 hdmi_write(hdmi, val, HDMI_TX_INVID0); in hdmi_video_sample()
174 hdmi_write(hdmi, val, HDMI_TX_INSTUFFING); in hdmi_video_sample()
175 hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0); in hdmi_video_sample()
176 hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1); in hdmi_video_sample()
177 hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0); in hdmi_video_sample()
178 hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1); in hdmi_video_sample()
179 hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0); in hdmi_video_sample()
180 hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1); in hdmi_video_sample()
183 static void hdmi_video_packetize(struct dw_hdmi *hdmi) in hdmi_video_packetize() argument
195 hdmi_write(hdmi, val, HDMI_VP_PR_CD); in hdmi_video_packetize()
197 hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK, in hdmi_video_packetize()
204 hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK | in hdmi_video_packetize()
207 hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, in hdmi_video_packetize()
210 hdmi_write(hdmi, remap_size, HDMI_VP_REMAP); in hdmi_video_packetize()
216 hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK | in hdmi_video_packetize()
220 hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK | in hdmi_video_packetize()
225 hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, in hdmi_video_packetize()
229 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit) in hdmi_phy_test_clear() argument
231 hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK, in hdmi_phy_test_clear()
235 static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec) in hdmi_phy_wait_i2c_done() argument
242 val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0); in hdmi_phy_wait_i2c_done()
244 hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0); in hdmi_phy_wait_i2c_done()
254 static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr) in hdmi_phy_i2c_write() argument
256 hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0); in hdmi_phy_i2c_write()
257 hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); in hdmi_phy_i2c_write()
258 hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR); in hdmi_phy_i2c_write()
259 hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR); in hdmi_phy_i2c_write()
260 hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, in hdmi_phy_i2c_write()
263 hdmi_phy_wait_i2c_done(hdmi, 1000); in hdmi_phy_i2c_write()
266 static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable) in hdmi_phy_enable_power() argument
268 hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK, in hdmi_phy_enable_power()
272 static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable) in hdmi_phy_enable_tmds() argument
274 hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK, in hdmi_phy_enable_tmds()
278 static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable) in hdmi_phy_enable_spare() argument
280 hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK, in hdmi_phy_enable_spare()
284 static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable) in hdmi_phy_gen2_pddq() argument
286 hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, in hdmi_phy_gen2_pddq()
290 static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable) in hdmi_phy_gen2_txpwron() argument
292 hdmi_mod(hdmi, HDMI_PHY_CONF0, in hdmi_phy_gen2_txpwron()
297 static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable) in hdmi_phy_sel_data_en_pol() argument
299 hdmi_mod(hdmi, HDMI_PHY_CONF0, in hdmi_phy_sel_data_en_pol()
304 static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, in hdmi_phy_sel_interface_control() argument
307 hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK, in hdmi_phy_sel_interface_control()
311 static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock) in hdmi_phy_configure() argument
316 if (!hdmi->mpll_cfg || !hdmi->phy_cfg) in hdmi_phy_configure()
320 hdmi_phy_gen2_txpwron(hdmi, 0); in hdmi_phy_configure()
323 hdmi_phy_gen2_pddq(hdmi, 1); in hdmi_phy_configure()
326 hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ); in hdmi_phy_configure()
327 hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ); in hdmi_phy_configure()
328 hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); in hdmi_phy_configure()
330 hdmi_phy_test_clear(hdmi, 1); in hdmi_phy_configure()
331 hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, in hdmi_phy_configure()
333 hdmi_phy_test_clear(hdmi, 0); in hdmi_phy_configure()
336 for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++) in hdmi_phy_configure()
337 if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock) in hdmi_phy_configure()
340 hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG); in hdmi_phy_configure()
341 hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL); in hdmi_phy_configure()
342 hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL); in hdmi_phy_configure()
344 hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL); in hdmi_phy_configure()
345 hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE); in hdmi_phy_configure()
347 for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++) in hdmi_phy_configure()
348 if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock) in hdmi_phy_configure()
356 hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM); in hdmi_phy_configure()
357 hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL); in hdmi_phy_configure()
358 hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL); in hdmi_phy_configure()
361 hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL); in hdmi_phy_configure()
363 hdmi_phy_enable_power(hdmi, 1); in hdmi_phy_configure()
366 hdmi_phy_enable_tmds(hdmi, 0); in hdmi_phy_configure()
367 hdmi_phy_enable_tmds(hdmi, 1); in hdmi_phy_configure()
370 hdmi_phy_gen2_txpwron(hdmi, 1); in hdmi_phy_configure()
371 hdmi_phy_gen2_pddq(hdmi, 0); in hdmi_phy_configure()
373 hdmi_phy_enable_spare(hdmi, 1); in hdmi_phy_configure()
378 val = hdmi_read(hdmi, HDMI_PHY_STAT0); in hdmi_phy_configure()
388 static void hdmi_av_composer(struct dw_hdmi *hdmi, in hdmi_av_composer() argument
424 hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF); in hdmi_av_composer()
427 hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1); in hdmi_av_composer()
428 hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0); in hdmi_av_composer()
431 hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1); in hdmi_av_composer()
432 hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0); in hdmi_av_composer()
435 hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1); in hdmi_av_composer()
436 hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0); in hdmi_av_composer()
439 hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK); in hdmi_av_composer()
442 hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1); in hdmi_av_composer()
443 hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0); in hdmi_av_composer()
446 hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY); in hdmi_av_composer()
449 hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1); in hdmi_av_composer()
450 hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0); in hdmi_av_composer()
453 hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH); in hdmi_av_composer()
457 static void hdmi_enable_video_path(struct dw_hdmi *hdmi, bool audio) in hdmi_enable_video_path() argument
462 hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR); in hdmi_enable_video_path()
463 hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR); in hdmi_enable_video_path()
464 hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC); in hdmi_enable_video_path()
467 hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM); in hdmi_enable_video_path()
468 hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM); in hdmi_enable_video_path()
469 hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM); in hdmi_enable_video_path()
471 hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, in hdmi_enable_video_path()
477 hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); in hdmi_enable_video_path()
480 hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); in hdmi_enable_video_path()
484 hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); in hdmi_enable_video_path()
489 static void hdmi_clear_overflow(struct dw_hdmi *hdmi) in hdmi_clear_overflow() argument
494 hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); in hdmi_clear_overflow()
496 val = hdmi_read(hdmi, HDMI_FC_INVIDCONF); in hdmi_clear_overflow()
499 hdmi_write(hdmi, val, HDMI_FC_INVIDCONF); in hdmi_clear_overflow()
502 static void hdmi_audio_set_format(struct dw_hdmi *hdmi) in hdmi_audio_set_format() argument
504 hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0, in hdmi_audio_set_format()
508 hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE | in hdmi_audio_set_format()
511 hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2); in hdmi_audio_set_format()
514 static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi) in hdmi_audio_fifo_reset() argument
516 hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ); in hdmi_audio_fifo_reset()
517 hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0); in hdmi_audio_fifo_reset()
519 hdmi_write(hdmi, 0x00, HDMI_AUD_INT); in hdmi_audio_fifo_reset()
520 hdmi_write(hdmi, 0x00, HDMI_AUD_INT1); in hdmi_audio_fifo_reset()
523 static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi) in hdmi_get_plug_in_status() argument
525 uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD; in hdmi_get_plug_in_status()
530 static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec) in hdmi_ddc_wait_i2c_done() argument
537 val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0); in hdmi_ddc_wait_i2c_done()
539 hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0); in hdmi_ddc_wait_i2c_done()
549 static void hdmi_ddc_reset(struct dw_hdmi *hdmi) in hdmi_ddc_reset() argument
551 hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0); in hdmi_ddc_reset()
554 static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff) in hdmi_read_edid() argument
562 hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); in hdmi_read_edid()
563 hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); in hdmi_read_edid()
564 hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE, in hdmi_read_edid()
567 hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE); in hdmi_read_edid()
568 hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR); in hdmi_read_edid()
569 hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR); in hdmi_read_edid()
575 hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS); in hdmi_read_edid()
578 hdmi_write(hdmi, HDMI_I2CM_OP_RD8, in hdmi_read_edid()
581 hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT, in hdmi_read_edid()
584 if (hdmi_ddc_wait_i2c_done(hdmi, 10)) { in hdmi_read_edid()
585 hdmi_ddc_reset(hdmi); in hdmi_read_edid()
590 buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI); in hdmi_read_edid()
635 int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) in dw_hdmi_phy_cfg() argument
641 hdmi_phy_sel_data_en_pol(hdmi, 1); in dw_hdmi_phy_cfg()
642 hdmi_phy_sel_interface_control(hdmi, 0); in dw_hdmi_phy_cfg()
643 hdmi_phy_enable_tmds(hdmi, 0); in dw_hdmi_phy_cfg()
644 hdmi_phy_enable_power(hdmi, 0); in dw_hdmi_phy_cfg()
646 ret = hdmi_phy_configure(hdmi, mpixelclock); in dw_hdmi_phy_cfg()
656 int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi) in dw_hdmi_phy_wait_for_hpd() argument
662 if (hdmi_get_plug_in_status(hdmi)) in dw_hdmi_phy_wait_for_hpd()
670 void dw_hdmi_phy_init(struct dw_hdmi *hdmi) in dw_hdmi_phy_init() argument
673 hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, in dw_hdmi_phy_init()
677 hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | in dw_hdmi_phy_init()
682 hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); in dw_hdmi_phy_init()
685 hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); in dw_hdmi_phy_init()
688 int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size) in dw_hdmi_read_edid() argument
697 ret = hdmi_read_edid(hdmi, 0, buf); in dw_hdmi_read_edid()
704 hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE); in dw_hdmi_read_edid()
712 int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) in dw_hdmi_enable() argument
720 hdmi_av_composer(hdmi, edid); in dw_hdmi_enable()
722 ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
726 hdmi_enable_video_path(hdmi, edid->hdmi_monitor); in dw_hdmi_enable()
729 hdmi_audio_fifo_reset(hdmi); in dw_hdmi_enable()
730 hdmi_audio_set_format(hdmi); in dw_hdmi_enable()
731 hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); in dw_hdmi_enable()
734 hdmi_video_packetize(hdmi); in dw_hdmi_enable()
735 hdmi_video_sample(hdmi); in dw_hdmi_enable()
737 hdmi_clear_overflow(hdmi); in dw_hdmi_enable()
742 void dw_hdmi_init(struct dw_hdmi *hdmi) in dw_hdmi_init() argument
757 hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE); in dw_hdmi_init()
760 hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT); in dw_hdmi_init()
763 hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT); in dw_hdmi_init()