Lines Matching refs:cfg
105 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
108 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | in exynos_fimd_set_dualrgb()
112 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
116 writel(cfg, ®->dualrgb); in exynos_fimd_set_dualrgb()
123 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
126 cfg = EXYNOS_DP_CLK_ENABLE; in exynos_fimd_set_dp_clkcon()
128 writel(cfg, ®->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()
135 unsigned int cfg = 0; in exynos_fimd_set_par() local
138 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_set_par()
141 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | in exynos_fimd_set_par()
147 cfg |= EXYNOS_WINCON_DATAPATH_DMA; in exynos_fimd_set_par()
149 cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; in exynos_fimd_set_par()
152 cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; in exynos_fimd_set_par()
156 cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; in exynos_fimd_set_par()
159 cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; in exynos_fimd_set_par()
163 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_set_par()
167 cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0); in exynos_fimd_set_par()
168 writel(cfg, (unsigned int)®->vidosd0a + in exynos_fimd_set_par()
171 cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) | in exynos_fimd_set_par()
176 writel(cfg, (unsigned int)®->vidosd0b + in exynos_fimd_set_par()
180 cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row); in exynos_fimd_set_par()
181 writel(cfg, (unsigned int)®->vidosd0c + in exynos_fimd_set_par()
205 unsigned int cfg = 0, div = 0, remainder, remainder_div; in exynos_fimd_set_clock() local
228 cfg = readl(®->vidcon0); in exynos_fimd_set_clock()
229 cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK | in exynos_fimd_set_clock()
232 cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | in exynos_fimd_set_clock()
252 cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1); in exynos_fimd_set_clock()
253 writel(cfg, ®->vidcon0); in exynos_fimd_set_clock()
259 unsigned int cfg = 0; in exynos_set_trigger() local
261 cfg = readl(®->trigcon); in exynos_set_trigger()
263 cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG); in exynos_set_trigger()
265 writel(cfg, ®->trigcon); in exynos_set_trigger()
271 unsigned int cfg = 0; in exynos_is_i80_frame_done() local
274 cfg = readl(®->trigcon); in exynos_is_i80_frame_done()
277 status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) == in exynos_is_i80_frame_done()
286 unsigned int cfg = 0; in exynos_fimd_lcd_on() local
289 cfg = readl(®->vidcon0); in exynos_fimd_lcd_on()
290 cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE); in exynos_fimd_lcd_on()
291 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_on()
298 unsigned int cfg = 0; in exynos_fimd_window_on() local
301 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_window_on()
303 cfg |= EXYNOS_WINCON_ENWIN_ENABLE; in exynos_fimd_window_on()
304 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_window_on()
307 cfg = readl(®->winshmap); in exynos_fimd_window_on()
308 cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id); in exynos_fimd_window_on()
309 writel(cfg, ®->winshmap); in exynos_fimd_window_on()
315 unsigned int cfg = 0; in exynos_fimd_lcd_off() local
317 cfg = readl(®->vidcon0); in exynos_fimd_lcd_off()
318 cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); in exynos_fimd_lcd_off()
319 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_off()
325 unsigned int cfg = 0; in exynos_fimd_window_off() local
327 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_window_off()
329 cfg &= EXYNOS_WINCON_ENWIN_DISABLE; in exynos_fimd_window_off()
330 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_window_off()
333 cfg = readl(®->winshmap); in exynos_fimd_window_off()
334 cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id); in exynos_fimd_window_off()
335 writel(cfg, ®->winshmap); in exynos_fimd_window_off()
381 unsigned int cfg = 0, rgb_mode; in exynos_fimd_lcd_init() local
394 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB; in exynos_fimd_lcd_init()
395 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_init()
397 cfg = readl(®->vidcon2); in exynos_fimd_lcd_init()
398 cfg &= ~(EXYNOS_VIDCON2_WB_MASK | in exynos_fimd_lcd_init()
401 cfg |= EXYNOS_VIDCON2_WB_DISABLE; in exynos_fimd_lcd_init()
402 writel(cfg, ®->vidcon2); in exynos_fimd_lcd_init()
405 cfg = 0; in exynos_fimd_lcd_init()
407 cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE; in exynos_fimd_lcd_init()
409 cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT; in exynos_fimd_lcd_init()
411 cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT; in exynos_fimd_lcd_init()
413 cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; in exynos_fimd_lcd_init()
415 writel(cfg, (unsigned int)®->vidcon1 + offset); in exynos_fimd_lcd_init()
418 cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1); in exynos_fimd_lcd_init()
419 cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1); in exynos_fimd_lcd_init()
420 cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1); in exynos_fimd_lcd_init()
421 writel(cfg, (unsigned int)®->vidtcon0 + offset); in exynos_fimd_lcd_init()
423 cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1); in exynos_fimd_lcd_init()
424 cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1); in exynos_fimd_lcd_init()
425 cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1); in exynos_fimd_lcd_init()
427 writel(cfg, (unsigned int)®->vidtcon1 + offset); in exynos_fimd_lcd_init()
430 cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) | in exynos_fimd_lcd_init()
435 writel(cfg, (unsigned int)®->vidtcon2 + offset); in exynos_fimd_lcd_init()
439 cfg = readl(®->vidcon0); in exynos_fimd_lcd_init()
440 cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK; in exynos_fimd_lcd_init()
441 cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT); in exynos_fimd_lcd_init()
442 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_init()
451 cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col * in exynos_fimd_lcd_init()
458 writel(cfg, (unsigned int)®->vidw00add2 + in exynos_fimd_lcd_init()