Lines Matching refs:IPU_BASE
101 #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
102 #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
103 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
104 #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
105 #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
106 #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
107 #define IPU_TASKS_STAT (0x1C + IPU_BASE)
108 #define IPU_IMA_ADDR (0x20 + IPU_BASE)
109 #define IPU_IMA_DATA (0x24 + IPU_BASE)
110 #define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
111 #define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
112 #define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
113 #define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
114 #define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
115 #define IPU_INT_STAT_1 (0x3C + IPU_BASE)
116 #define IPU_INT_STAT_2 (0x40 + IPU_BASE)
117 #define IPU_INT_STAT_3 (0x44 + IPU_BASE)
118 #define IPU_INT_STAT_4 (0x48 + IPU_BASE)
119 #define IPU_INT_STAT_5 (0x4C + IPU_BASE)
120 #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
121 #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
122 #define IPU_BRK_STAT (0x58 + IPU_BASE)
123 #define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
126 #define IC_CONF (0x88 + IPU_BASE)
127 #define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
128 #define IC_PRP_VF_RSC (0x90 + IPU_BASE)
129 #define IC_PP_RSC (0x94 + IPU_BASE)
130 #define IC_CMBP_1 (0x98 + IPU_BASE)
131 #define IC_CMBP_2 (0x9C + IPU_BASE)
132 #define PF_CONF (0xA0 + IPU_BASE)
133 #define IDMAC_CONF (0xA4 + IPU_BASE)
134 #define IDMAC_CHA_EN (0xA8 + IPU_BASE)
135 #define IDMAC_CHA_PRI (0xAC + IPU_BASE)
136 #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
158 #define SDC_COM_CONF (0xB4 + IPU_BASE)
159 #define SDC_GW_CTRL (0xB8 + IPU_BASE)
160 #define SDC_FG_POS (0xBC + IPU_BASE)
161 #define SDC_BG_POS (0xC0 + IPU_BASE)
162 #define SDC_CUR_POS (0xC4 + IPU_BASE)
163 #define SDC_PWM_CTRL (0xC8 + IPU_BASE)
164 #define SDC_CUR_MAP (0xCC + IPU_BASE)
165 #define SDC_HOR_CONF (0xD0 + IPU_BASE)
166 #define SDC_VER_CONF (0xD4 + IPU_BASE)
167 #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
168 #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
182 #define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
183 #define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
184 #define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
185 #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
186 #define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
187 #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
188 #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
189 #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
190 #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
191 #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
192 #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
193 #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
194 #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
195 #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
196 #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
197 #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
198 #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
199 #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
200 #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
201 #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
202 #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
203 #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
204 #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
205 #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
206 #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
207 #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
208 #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
209 #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
210 #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
211 #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
212 #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
213 #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
214 #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
215 #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
216 #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
217 #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
218 #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
219 #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
220 #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)