30 void lcdc_init(struct sunxi_lcdc_reg * const lcdc)  in lcdc_init()  argument
33 	writel(0, &lcdc->ctrl); /* Disable tcon */  in lcdc_init()
34 	writel(0, &lcdc->int0); /* Disable all interrupts */  in lcdc_init()
37 	clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);  in lcdc_init()
40 	writel(0xffffffff, &lcdc->tcon0_io_tristate);  in lcdc_init()
41 	writel(0xffffffff, &lcdc->tcon1_io_tristate);  in lcdc_init()
44 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)  in lcdc_enable()  argument
46 	setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);  in lcdc_enable()
48 	setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);  in lcdc_enable()
49 	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);  in lcdc_enable()
52 	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);  in lcdc_enable()
54 	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);  in lcdc_enable()
56 		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));  in lcdc_enable()
58 		setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));  in lcdc_enable()
60 	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);  in lcdc_enable()
62 	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);  in lcdc_enable()
64 	setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);  in lcdc_enable()
65 	setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);  in lcdc_enable()
70 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,  in lcdc_tcon0_mode_set()  argument
79 	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,  in lcdc_tcon0_mode_set()
85 	       SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);  in lcdc_tcon0_mode_set()
88 	       SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);  in lcdc_tcon0_mode_set()
91 	       SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active);  in lcdc_tcon0_mode_set()
96 	       SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);  in lcdc_tcon0_mode_set()
101 	       SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);  in lcdc_tcon0_mode_set()
105 	       SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);  in lcdc_tcon0_mode_set()
107 	writel(0, &lcdc->tcon0_hv_intf);  in lcdc_tcon0_mode_set()
108 	writel(0, &lcdc->tcon0_cpu_intf);  in lcdc_tcon0_mode_set()
113 	       SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);  in lcdc_tcon0_mode_set()
117 		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);  in lcdc_tcon0_mode_set()
118 		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);  in lcdc_tcon0_mode_set()
119 		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);  in lcdc_tcon0_mode_set()
120 		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);  in lcdc_tcon0_mode_set()
121 		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);  in lcdc_tcon0_mode_set()
122 		writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);  in lcdc_tcon0_mode_set()
123 		writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);  in lcdc_tcon0_mode_set()
124 		writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);  in lcdc_tcon0_mode_set()
125 		writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);  in lcdc_tcon0_mode_set()
126 		writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);  in lcdc_tcon0_mode_set()
130 		       &lcdc->tcon0_frm_ctrl);  in lcdc_tcon0_mode_set()
143 	writel(val, &lcdc->tcon0_io_polarity);  in lcdc_tcon0_mode_set()
145 	writel(0, &lcdc->tcon0_io_tristate);  in lcdc_tcon0_mode_set()
148 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,  in lcdc_tcon1_mode_set()  argument
156 	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,  in lcdc_tcon1_mode_set()
164 	       SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);  in lcdc_tcon1_mode_set()
170 	       &lcdc->tcon1_timing_source);  in lcdc_tcon1_mode_set()
172 	       &lcdc->tcon1_timing_scale);  in lcdc_tcon1_mode_set()
174 	       &lcdc->tcon1_timing_out);  in lcdc_tcon1_mode_set()
179 	       SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);  in lcdc_tcon1_mode_set()
186 	       SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);  in lcdc_tcon1_mode_set()
189 	       SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync);  in lcdc_tcon1_mode_set()
197 		writel(val, &lcdc->tcon1_io_polarity);  in lcdc_tcon1_mode_set()
199 		clrbits_le32(&lcdc->tcon1_io_tristate,  in lcdc_tcon1_mode_set()
206 		clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,  in lcdc_tcon1_mode_set()