91 	struct sunxi_ccm_reg * const ccm =  in sunxi_hdmi_hpd_detect()  local
101 	clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,  in sunxi_hdmi_hpd_detect()
106 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);  in sunxi_hdmi_hpd_detect()
108 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);  in sunxi_hdmi_hpd_detect()
111 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);  in sunxi_hdmi_hpd_detect()
126 	struct sunxi_ccm_reg * const ccm =  in sunxi_hdmi_shutdown()  local
132 	clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);  in sunxi_hdmi_shutdown()
133 	clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);  in sunxi_hdmi_shutdown()
135 	clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);  in sunxi_hdmi_shutdown()
214 	struct sunxi_ccm_reg * const ccm =  in sunxi_hdmi_edid_get_mode()  local
226 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);  in sunxi_hdmi_edid_get_mode()
263 	clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);  in sunxi_hdmi_edid_get_mode()
343 	struct sunxi_ccm_reg * const ccm =  in sunxi_frontend_init()  local
350 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0);  in sunxi_frontend_init()
351 	setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0);  in sunxi_frontend_init()
352 	clock_set_de_mod_clock(&ccm->fe0_clk_cfg, 300000000);  in sunxi_frontend_init()
436 	struct sunxi_ccm_reg * const ccm =  in sunxi_composer_init()  local
446 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);  in sunxi_composer_init()
450 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);  in sunxi_composer_init()
452 	setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);  in sunxi_composer_init()
454 	clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);  in sunxi_composer_init()
521 	struct sunxi_ccm_reg * const ccm =  in sunxi_lcdc_init()  local
528 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);  in sunxi_lcdc_init()
530 	setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);  in sunxi_lcdc_init()
534 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);  in sunxi_lcdc_init()
537 	setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS);  in sunxi_lcdc_init()
539 	setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);  in sunxi_lcdc_init()
647 	struct sunxi_ccm_reg * const ccm =  local
668 	lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
683 	struct sunxi_ccm_reg * const ccm =  local
696 	lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
817 	struct sunxi_ccm_reg * const ccm =  local
823 	setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
825 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
856 	struct sunxi_ccm_reg * const ccm =  local
861 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
863 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
864 	clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);