211 		(struct edid_detailed_timing *)edid1.monitor_details.timing;  in sunxi_hdmi_edid_get_mode()
614 					      struct display_timing *timing)  in sunxi_ctfb_mode_to_display_timing()  argument
616 	timing->pixelclock.typ = mode->pixclock_khz * 1000;  in sunxi_ctfb_mode_to_display_timing()
618 	timing->hactive.typ = mode->xres;  in sunxi_ctfb_mode_to_display_timing()
619 	timing->hfront_porch.typ = mode->right_margin;  in sunxi_ctfb_mode_to_display_timing()
620 	timing->hback_porch.typ = mode->left_margin;  in sunxi_ctfb_mode_to_display_timing()
621 	timing->hsync_len.typ = mode->hsync_len;  in sunxi_ctfb_mode_to_display_timing()
623 	timing->vactive.typ = mode->yres;  in sunxi_ctfb_mode_to_display_timing()
624 	timing->vfront_porch.typ = mode->lower_margin;  in sunxi_ctfb_mode_to_display_timing()
625 	timing->vback_porch.typ = mode->upper_margin;  in sunxi_ctfb_mode_to_display_timing()
626 	timing->vsync_len.typ = mode->vsync_len;  in sunxi_ctfb_mode_to_display_timing()
628 	timing->flags = 0;  in sunxi_ctfb_mode_to_display_timing()
631 		timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;  in sunxi_ctfb_mode_to_display_timing()
633 		timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;  in sunxi_ctfb_mode_to_display_timing()
635 		timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;  in sunxi_ctfb_mode_to_display_timing()
637 		timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;  in sunxi_ctfb_mode_to_display_timing()
639 		timing->flags |= DISPLAY_FLAGS_INTERLACED;  in sunxi_ctfb_mode_to_display_timing()
650 	struct display_timing timing;  local
671 	sunxi_ctfb_mode_to_display_timing(mode, &timing);
672 	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
685 	struct display_timing timing;  local
687 	sunxi_ctfb_mode_to_display_timing(mode, &timing);
688 	lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,