Lines Matching refs:dp
41 static inline u32 tegra_dpaux_readl(struct tegra_dp_priv *dp, u32 reg) in tegra_dpaux_readl() argument
43 return readl((u32 *)dp->regs + reg); in tegra_dpaux_readl()
46 static inline void tegra_dpaux_writel(struct tegra_dp_priv *dp, u32 reg, in tegra_dpaux_writel() argument
49 writel(val, (u32 *)dp->regs + reg); in tegra_dpaux_writel()
52 static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dp_priv *dp, in tegra_dc_dpaux_poll_register() argument
62 reg_val = tegra_dpaux_readl(dp, reg); in tegra_dc_dpaux_poll_register()
76 static inline int tegra_dpaux_wait_transaction(struct tegra_dp_priv *dp) in tegra_dpaux_wait_transaction() argument
80 if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, in tegra_dpaux_wait_transaction()
90 static int tegra_dc_dpaux_write_chunk(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dpaux_write_chunk() argument
114 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); in tegra_dc_dpaux_write_chunk()
117 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data); in tegra_dc_dpaux_write_chunk()
121 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); in tegra_dc_dpaux_write_chunk()
133 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); in tegra_dc_dpaux_write_chunk()
135 if (tegra_dpaux_wait_transaction(dp)) in tegra_dc_dpaux_write_chunk()
138 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dc_dpaux_write_chunk()
148 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_write_chunk()
164 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_write_chunk()
187 static int tegra_dc_dpaux_read_chunk(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dpaux_read_chunk() argument
212 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dc_dpaux_read_chunk()
218 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); in tegra_dc_dpaux_read_chunk()
220 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); in tegra_dc_dpaux_read_chunk()
231 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); in tegra_dc_dpaux_read_chunk()
233 if (tegra_dpaux_wait_transaction(dp)) in tegra_dc_dpaux_read_chunk()
236 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dc_dpaux_read_chunk()
246 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_read_chunk()
262 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_read_chunk()
278 temp_data[i] = tegra_dpaux_readl(dp, in tegra_dc_dpaux_read_chunk()
296 static int tegra_dc_dpaux_read(struct tegra_dp_priv *dp, u32 cmd, u32 addr, in tegra_dc_dpaux_read() argument
308 ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, in tegra_dc_dpaux_read()
324 static int tegra_dc_dp_dpcd_read(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dp_dpcd_read() argument
331 ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, in tegra_dc_dp_dpcd_read()
341 static int tegra_dc_dp_dpcd_write(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dp_dpcd_write() argument
348 ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, in tegra_dc_dp_dpcd_write()
358 static int tegra_dc_i2c_aux_read(struct tegra_dp_priv *dp, u32 i2c_addr, in tegra_dc_i2c_aux_read() argument
369 dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr, in tegra_dc_i2c_aux_read()
378 dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr, in tegra_dc_i2c_aux_read()
394 static void tegra_dc_dpaux_enable(struct tegra_dp_priv *dp) in tegra_dc_dpaux_enable() argument
397 tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff); in tegra_dc_dpaux_enable()
399 tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0); in tegra_dc_dpaux_enable()
401 tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, in tegra_dc_dpaux_enable()
407 tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, in tegra_dc_dpaux_enable()
412 static void tegra_dc_dp_dump_link_cfg(struct tegra_dp_priv *dp, in tegra_dc_dp_dump_link_cfg() argument
449 static int _tegra_dp_lower_link_config(struct tegra_dp_priv *dp, in _tegra_dp_lower_link_config() argument
481 static int tegra_dc_dp_calc_config(struct tegra_dp_priv *dp, in tegra_dc_dp_calc_config() argument
645 tegra_dc_dp_dump_link_cfg(dp, link_cfg); in tegra_dc_dp_calc_config()
653 struct tegra_dp_priv *dp, in tegra_dc_dp_init_max_link_cfg() argument
662 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
673 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
679 ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL, in tegra_dc_dp_init_max_link_cfg()
683 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE, in tegra_dc_dp_init_max_link_cfg()
696 ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
712 tegra_dc_dp_calc_config(dp, timing, link_cfg); in tegra_dc_dp_init_max_link_cfg()
735 static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp, in tegra_dp_set_link_bandwidth() argument
742 return tegra_dc_dp_dpcd_write(dp, DP_LINK_BW_SET, link_bw); in tegra_dp_set_link_bandwidth()
745 static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp, in tegra_dp_set_lane_count() argument
756 ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data); in tegra_dp_set_lane_count()
766 static int tegra_dc_dp_link_trained(struct tegra_dp_priv *dp, in tegra_dc_dp_link_trained() argument
775 ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ? in tegra_dc_dp_link_trained()
793 static int tegra_dp_channel_eq_status(struct tegra_dp_priv *dp, in tegra_dp_channel_eq_status() argument
803 ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data); in tegra_dp_channel_eq_status()
825 ret = tegra_dc_dp_dpcd_read(dp, in tegra_dp_channel_eq_status()
837 static int tegra_dp_clock_recovery_status(struct tegra_dp_priv *dp, in tegra_dp_clock_recovery_status() argument
846 ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt), in tegra_dp_clock_recovery_status()
862 static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_lt_adjust() argument
872 ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt, in tegra_dp_lt_adjust()
888 ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2, in tegra_dp_lt_adjust()
902 static void tegra_dp_wait_aux_training(struct tegra_dp_priv *dp, in tegra_dp_wait_aux_training() argument
912 static void tegra_dp_tpg(struct tegra_dp_priv *dp, u32 tp, u32 n_lanes, in tegra_dp_tpg() argument
919 tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg); in tegra_dp_tpg()
920 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, data); in tegra_dp_tpg()
923 static int tegra_dp_link_config(struct tegra_dp_priv *dp, in tegra_dp_link_config() argument
936 ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data); in tegra_dp_link_config()
945 ret = tegra_dc_dp_dpcd_write(dp, DP_SET_POWER, in tegra_dp_link_config()
958 ret = tegra_dc_dp_set_assr(dp, dp->sor, 1); in tegra_dp_link_config()
963 ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw); in tegra_dp_link_config()
968 ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor); in tegra_dp_link_config()
973 tegra_dc_sor_set_dp_linkctl(dp->sor, 1, training_pattern_none, in tegra_dp_link_config()
979 static int tegra_dp_lower_link_config(struct tegra_dp_priv *dp, in tegra_dp_lower_link_config() argument
989 ret = _tegra_dp_lower_link_config(dp, cfg); in tegra_dp_lower_link_config()
991 ret = tegra_dc_dp_calc_config(dp, timing, cfg); in tegra_dp_lower_link_config()
993 ret = tegra_dp_link_config(dp, cfg); in tegra_dp_lower_link_config()
1001 tegra_dp_link_config(dp, &tmp_cfg); in tegra_dp_lower_link_config()
1005 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_lt_config() argument
1008 struct udevice *sor = dp->sor; in tegra_dp_lt_config()
1050 tegra_dp_disable_tx_pu(dp->sor); in tegra_dp_lt_config()
1065 tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val); in tegra_dp_lt_config()
1081 tegra_dc_dp_dpcd_write(dp, in tegra_dp_lt_config()
1090 static int _tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], in _tegra_dp_channel_eq() argument
1101 ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, in _tegra_dp_channel_eq()
1105 tegra_dp_lt_config(dp, pe, vs, pc, cfg); in _tegra_dp_channel_eq()
1108 tegra_dp_wait_aux_training(dp, false, cfg); in _tegra_dp_channel_eq()
1110 if (!tegra_dp_clock_recovery_status(dp, cfg)) { in _tegra_dp_channel_eq()
1115 if (!tegra_dp_channel_eq_status(dp, cfg)) in _tegra_dp_channel_eq()
1122 static int tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_channel_eq() argument
1134 tegra_dp_tpg(dp, tp_src, n_lanes, cfg); in tegra_dp_channel_eq()
1136 ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg); in tegra_dp_channel_eq()
1138 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg); in tegra_dp_channel_eq()
1143 static int _tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], in _tegra_dp_clk_recovery() argument
1152 tegra_dp_lt_config(dp, pe, vs, pc, cfg); in _tegra_dp_clk_recovery()
1153 tegra_dp_wait_aux_training(dp, true, cfg); in _tegra_dp_clk_recovery()
1155 if (tegra_dp_clock_recovery_status(dp, cfg)) in _tegra_dp_clk_recovery()
1159 tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, cfg); in _tegra_dp_clk_recovery()
1170 static int tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], in tegra_dp_clk_recovery() argument
1178 tegra_dp_tpg(dp, training_pattern_1, n_lanes, cfg); in tegra_dp_clk_recovery()
1180 err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes, in tegra_dp_clk_recovery()
1183 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg); in tegra_dp_clk_recovery()
1188 static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp, in tegra_dc_dp_full_link_training() argument
1192 struct udevice *sor = dp->sor; in tegra_dc_dp_full_link_training()
1203 err = tegra_dp_clk_recovery(dp, pe, vs, pc, cfg); in tegra_dc_dp_full_link_training()
1205 if (!tegra_dp_lower_link_config(dp, timing, cfg)) in tegra_dc_dp_full_link_training()
1212 err = tegra_dp_channel_eq(dp, pe, vs, pc, cfg); in tegra_dc_dp_full_link_training()
1214 if (!tegra_dp_lower_link_config(dp, timing, cfg)) in tegra_dc_dp_full_link_training()
1221 tegra_dc_dp_dump_link_cfg(dp, cfg); in tegra_dc_dp_full_link_training()
1233 static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp, in tegra_dc_dp_fast_link_training() argument
1247 tegra_dc_dp_dpcd_write(dp, DP_MAIN_LINK_CHANNEL_CODING_SET, in tegra_dc_dp_fast_link_training()
1252 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, in tegra_dc_dp_fast_link_training()
1256 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); in tegra_dc_dp_fast_link_training()
1260 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, in tegra_dc_dp_fast_link_training()
1270 tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena); in tegra_dc_dp_fast_link_training()
1273 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, in tegra_dc_dp_fast_link_training()
1276 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); in tegra_dc_dp_fast_link_training()
1280 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, DP_LANE0_1_STATUS, in tegra_dc_dp_fast_link_training()
1289 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, 0); in tegra_dc_dp_fast_link_training()
1291 if (tegra_dc_dp_link_trained(dp, link_cfg)) { in tegra_dc_dp_fast_link_training()
1304 static int tegra_dp_do_link_training(struct tegra_dp_priv *dp, in tegra_dp_do_link_training() argument
1314 ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor); in tegra_dp_do_link_training()
1322 ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg); in tegra_dp_do_link_training()
1331 ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg); in tegra_dp_do_link_training()
1348 static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp, in tegra_dc_dp_explore_link_cfg() argument
1375 if ((!tegra_dc_dp_calc_config(dp, timing, &temp_cfg)) && in tegra_dc_dp_explore_link_cfg()
1376 (!tegra_dp_link_config(dp, &temp_cfg)) && in tegra_dc_dp_explore_link_cfg()
1377 (!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor))) in tegra_dc_dp_explore_link_cfg()
1384 static int tegra_dp_hpd_plug(struct tegra_dp_priv *dp) in tegra_dp_hpd_plug() argument
1392 val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dp_hpd_plug()
1401 static int tegra_dc_dp_sink_out_of_sync(struct tegra_dp_priv *dp, u32 delay_ms) in tegra_dc_dp_sink_out_of_sync() argument
1409 ret = tegra_dc_dp_dpcd_read(dp, DP_SINK_STATUS, &dpcd_data); in tegra_dc_dp_sink_out_of_sync()
1422 static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp, in tegra_dc_dp_check_sink() argument
1441 if (!tegra_dc_dp_sink_out_of_sync(dp, link_cfg->frame_in_ms * in tegra_dc_dp_check_sink()
1450 ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor); in tegra_dc_dp_check_sink()
1453 if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor, in tegra_dc_dp_check_sink()
1459 tegra_dc_sor_set_power_state(dp->sor, 1); in tegra_dc_dp_check_sink()
1460 tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing); in tegra_dc_dp_check_sink()