555 #define UTCR1_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \  argument
556 			(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
558 #define UTCR2_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \  argument
559 			(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
563 #define UTCR1_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
564 			(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
566 #define UTCR2_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
567 			(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
713 #define SDCR3_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \  argument
714 			(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
716 #define SDCR4_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \  argument
717 			(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
721 #define SDCR3_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
722 			(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
724 #define SDCR4_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
725 			(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
910 #define MCCR0_AudSmpDiv(Div)		/*  Audio Sampling rate Divisor    */ \  argument
912 			((Div)/32 << FShft (MCCR0_ASD))
915 #define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \  argument
916 			(((Div) + 31)/32 << FShft (MCCR0_ASD))
923 #define MCCR0_TcmSmpDiv(Div)		/*  Telecom Sampling rate Divisor  */ \  argument
925 			((Div)/32 << FShft (MCCR0_TSD))
928 #define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \  argument
929 			(((Div) + 31)/32 << FShft (MCCR0_TSD))
950 #define MCCR0_ExtClkDiv(Div)		/*  External Clock Divisor [1..4]  */ \  argument
951 			(((Div) - 1) << FShft (MCCR0_ECP))
1054 #define SSCR0_SerClkDiv(Div)		/*  Serial Clock Divisor [2..512]  */ \  argument
1055 			(((Div) - 2)/2 << FShft (SSCR0_SCR))
1058 #define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \  argument
1059 			(((Div) - 1)/2 << FShft (SSCR0_SCR))
2785 #define LCCR3_PixClkDiv(Div)		/*  Pixel Clock Divisor [6..514]   */ \  argument
2786 			(((Div) - 4)/2 << FShft (LCCR3_PCD))
2789 #define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \  argument
2790 			(((Div) - 3)/2 << FShft (LCCR3_PCD))
2795 #define LCCR3_ACBsDiv(Div)		/*  AC Bias clock Divisor [2..512] */ \  argument
2796 			(((Div) - 2)/2 << FShft (LCCR3_ACB))
2799 #define LCCR3_CeilACBsDiv(Div)		/*  Ceil. of ACBsDiv [2..512]	   */ \  argument
2800 			(((Div) - 1)/2 << FShft (LCCR3_ACB))