Lines Matching refs:Nb
73 #define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ argument
74 (0x00000000 + (Nb)*StMemBnkSp)
90 #define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ argument
91 (0xC0000000 + (Nb)*DRAMBnkSp)
136 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
137 (0x20000000 + (Nb)*PCMCIASp)
138 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ argument
139 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ argument
140 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
141 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ argument
142 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
410 #define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ argument
411 (0x80010000 + ((Nb) - 1)*0x00020000)
412 #define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ argument
413 (0x80010004 + ((Nb) - 1)*0x00020000)
414 #define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ argument
415 (0x80010008 + ((Nb) - 1)*0x00020000)
416 #define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ argument
417 (0x8001000C + ((Nb) - 1)*0x00020000)
418 #define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ argument
419 (0x80010010 + ((Nb) - 1)*0x00020000)
420 #define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ argument
421 (0x80010014 + ((Nb) - 1)*0x00020000)
422 #define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ argument
423 (0x8001001C + ((Nb) - 1)*0x00020000)
424 #define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ argument
425 (0x80010020 + ((Nb) - 1)*0x00020000)
1114 #define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ argument
1115 (0x90000000 + (Nb)*4)
1142 #define OSSR_M(Nb) /* Match detected [0..3] */ \ argument
1143 (0x00000001 << (Nb))
1152 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ argument
1153 (0x00000001 << (Nb))
1276 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ argument
1533 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ argument
1534 (0x00000001 << (Nb))
1564 #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ argument
1565 GPIO_GPIO ((Nb) - 6)
1648 #define IC_GPIO(Nb) /* GPIO [0..10] */ \ argument
1649 (0x00000001 << (Nb))
1670 #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ argument
1671 (0x00100000 << (Nb))
1678 #define IC_OST(Nb) /* OS Timer match [0..3] */ \ argument
1679 (0x04000000 << (Nb))
1735 #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ argument
1736 (0x00000001 << (Nb))
1816 #define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ argument
1817 (0xA0000004 + (Nb)*4)
1839 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ argument
1840 (0x00000001 << (Nb))
1909 #define _MSC(Nb) /* Static memory Control reg. */ \ argument
1911 (0xA0000010 + (Nb)*4)
1933 #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ argument
1934 Fld (16, ((Nb) Modulo 2)*16)
2009 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
2010 Fld (15, (Nb)*16)
2148 #define _DDAR(Nb) /* DMA Device Address Reg. */ \ argument
2150 (0xB0000000 + (Nb)*DMASp)
2151 #define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ argument
2153 (0xB0000004 + (Nb)*DMASp)
2154 #define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ argument
2156 (0xB0000008 + (Nb)*DMASp)
2157 #define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ argument
2159 (0xB000000C + (Nb)*DMASp)
2160 #define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ argument
2162 (0xB0000010 + (Nb)*DMASp)
2163 #define _DBTA(Nb) /* DMA Buffer Transfer count */ \ argument
2165 (0xB0000014 + (Nb)*DMASp)
2166 #define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ argument
2168 (0xB0000018 + (Nb)*DMASp)
2169 #define _DBTB(Nb) /* DMA Buffer Transfer count */ \ argument
2171 (0xB000001C + (Nb)*DMASp)