293 struct tsec {  struct
295 	u32	res000[4];
297 	u32	ievent;		/* Interrupt Event */
298 	u32	imask;		/* Interrupt Mask */
299 	u32	edis;		/* Error Disabled */
300 	u32	res01c;
301 	u32	ecntrl;		/* Ethernet Control */
302 	u32	minflr;		/* Minimum Frame Length */
303 	u32	ptv;		/* Pause Time Value */
304 	u32	dmactrl;	/* DMA Control */
305 	u32	tbipa;		/* TBI PHY Address */
307 	u32	res034[3];
308 	u32	res040[48];
311 	u32	tctrl;		/* Transmit Control */
312 	u32	tstat;		/* Transmit Status */
313 	u32	res108;
314 	u32	tbdlen;		/* Tx BD Data Length */
315 	u32	res110[5];
316 	u32	ctbptr;		/* Current TxBD Pointer */
317 	u32	res128[23];
318 	u32	tbptr;		/* TxBD Pointer */
319 	u32	res188[30];
321 	u32	res200;
322 	u32	tbase;		/* TxBD Base Address */
323 	u32	res208[42];
324 	u32	ostbd;		/* Out of Sequence TxBD */
325 	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
326 	u32	res2b8[18];
329 	u32	rctrl;		/* Receive Control */
330 	u32	rstat;		/* Receive Status */
331 	u32	res308;
332 	u32	rbdlen;		/* RxBD Data Length */
333 	u32	res310[4];
334 	u32	res320;
335 	u32	crbptr;		/* Current Receive Buffer Pointer */
336 	u32	res328[6];
337 	u32	mrblr;		/* Maximum Receive Buffer Length */
338 	u32	res344[16];
339 	u32	rbptr;		/* RxBD Pointer */
340 	u32	res388[30];
342 	u32	res400;
343 	u32	rbase;		/* RxBD Base Address */
344 	u32	res408[62];
370 	struct tsec_rmon_mib	rmon;  argument
374 	struct tsec_hash_regs	hash;  argument
398 	struct tsec __iomem *regs;  argument