Lines Matching refs:vn
1820 void Assembler::NEON3DifferentL(const VRegister& vd, const VRegister& vn, in NEON3DifferentL() argument
1822 DCHECK(AreSameFormat(vn, vm)); in NEON3DifferentL()
1823 DCHECK((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) || in NEON3DifferentL()
1824 (vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) || in NEON3DifferentL()
1825 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) || in NEON3DifferentL()
1826 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); in NEON3DifferentL()
1830 format = SFormat(vn); in NEON3DifferentL()
1832 format = VFormat(vn); in NEON3DifferentL()
1834 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3DifferentL()
1837 void Assembler::NEON3DifferentW(const VRegister& vd, const VRegister& vn, in NEON3DifferentW() argument
1839 DCHECK(AreSameFormat(vd, vn)); in NEON3DifferentW()
1843 Emit(VFormat(vm) | vop | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3DifferentW()
1846 void Assembler::NEON3DifferentHN(const VRegister& vd, const VRegister& vn, in NEON3DifferentHN() argument
1848 DCHECK(AreSameFormat(vm, vn)); in NEON3DifferentHN()
1849 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) || in NEON3DifferentHN()
1850 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEON3DifferentHN()
1851 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D())); in NEON3DifferentHN()
1852 Emit(VFormat(vd) | vop | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3DifferentHN()
1856 V(pmull, NEON_PMULL, vn.IsVector() && vn.Is8B()) \
1857 V(pmull2, NEON_PMULL2, vn.IsVector() && vn.Is16B()) \
1858 V(saddl, NEON_SADDL, vn.IsVector() && vn.IsD()) \
1859 V(saddl2, NEON_SADDL2, vn.IsVector() && vn.IsQ()) \
1860 V(sabal, NEON_SABAL, vn.IsVector() && vn.IsD()) \
1861 V(sabal2, NEON_SABAL2, vn.IsVector() && vn.IsQ()) \
1862 V(uabal, NEON_UABAL, vn.IsVector() && vn.IsD()) \
1863 V(uabal2, NEON_UABAL2, vn.IsVector() && vn.IsQ()) \
1864 V(sabdl, NEON_SABDL, vn.IsVector() && vn.IsD()) \
1865 V(sabdl2, NEON_SABDL2, vn.IsVector() && vn.IsQ()) \
1866 V(uabdl, NEON_UABDL, vn.IsVector() && vn.IsD()) \
1867 V(uabdl2, NEON_UABDL2, vn.IsVector() && vn.IsQ()) \
1868 V(smlal, NEON_SMLAL, vn.IsVector() && vn.IsD()) \
1869 V(smlal2, NEON_SMLAL2, vn.IsVector() && vn.IsQ()) \
1870 V(umlal, NEON_UMLAL, vn.IsVector() && vn.IsD()) \
1871 V(umlal2, NEON_UMLAL2, vn.IsVector() && vn.IsQ()) \
1872 V(smlsl, NEON_SMLSL, vn.IsVector() && vn.IsD()) \
1873 V(smlsl2, NEON_SMLSL2, vn.IsVector() && vn.IsQ()) \
1874 V(umlsl, NEON_UMLSL, vn.IsVector() && vn.IsD()) \
1875 V(umlsl2, NEON_UMLSL2, vn.IsVector() && vn.IsQ()) \
1876 V(smull, NEON_SMULL, vn.IsVector() && vn.IsD()) \
1877 V(smull2, NEON_SMULL2, vn.IsVector() && vn.IsQ()) \
1878 V(umull, NEON_UMULL, vn.IsVector() && vn.IsD()) \
1879 V(umull2, NEON_UMULL2, vn.IsVector() && vn.IsQ()) \
1880 V(ssubl, NEON_SSUBL, vn.IsVector() && vn.IsD()) \
1881 V(ssubl2, NEON_SSUBL2, vn.IsVector() && vn.IsQ()) \
1882 V(uaddl, NEON_UADDL, vn.IsVector() && vn.IsD()) \
1883 V(uaddl2, NEON_UADDL2, vn.IsVector() && vn.IsQ()) \
1884 V(usubl, NEON_USUBL, vn.IsVector() && vn.IsD()) \
1885 V(usubl2, NEON_USUBL2, vn.IsVector() && vn.IsQ()) \
1886 V(sqdmlal, NEON_SQDMLAL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1887 V(sqdmlal2, NEON_SQDMLAL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
1888 V(sqdmlsl, NEON_SQDMLSL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1889 V(sqdmlsl2, NEON_SQDMLSL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
1890 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1891 V(sqdmull2, NEON_SQDMULL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S())
1894 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
1897 NEON3DifferentL(vd, vn, vm, OP); \
1913 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
1916 NEON3DifferentHN(vd, vn, vm, OP); \
1921 void Assembler::NEONPerm(const VRegister& vd, const VRegister& vn, in NEON_3DIFF_HN_LIST()
1923 DCHECK(AreSameFormat(vd, vn, vm)); in NEON_3DIFF_HN_LIST()
1925 Emit(VFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON_3DIFF_HN_LIST()
1928 void Assembler::trn1(const VRegister& vd, const VRegister& vn, in trn1() argument
1930 NEONPerm(vd, vn, vm, NEON_TRN1); in trn1()
1933 void Assembler::trn2(const VRegister& vd, const VRegister& vn, in trn2() argument
1935 NEONPerm(vd, vn, vm, NEON_TRN2); in trn2()
1938 void Assembler::uzp1(const VRegister& vd, const VRegister& vn, in uzp1() argument
1940 NEONPerm(vd, vn, vm, NEON_UZP1); in uzp1()
1943 void Assembler::uzp2(const VRegister& vd, const VRegister& vn, in uzp2() argument
1945 NEONPerm(vd, vn, vm, NEON_UZP2); in uzp2()
1948 void Assembler::zip1(const VRegister& vd, const VRegister& vn, in zip1() argument
1950 NEONPerm(vd, vn, vm, NEON_ZIP1); in zip1()
1953 void Assembler::zip2(const VRegister& vd, const VRegister& vn, in zip2() argument
1955 NEONPerm(vd, vn, vm, NEON_ZIP2); in zip2()
1958 void Assembler::NEONShiftImmediate(const VRegister& vd, const VRegister& vn, in NEONShiftImmediate() argument
1960 DCHECK(AreSameFormat(vd, vn)); in NEONShiftImmediate()
1962 if (vn.IsScalar()) { in NEONShiftImmediate()
1969 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd)); in NEONShiftImmediate()
1972 void Assembler::NEONShiftLeftImmediate(const VRegister& vd, const VRegister& vn, in NEONShiftLeftImmediate() argument
1974 int laneSizeInBits = vn.LaneSizeInBits(); in NEONShiftLeftImmediate()
1976 NEONShiftImmediate(vd, vn, op, (laneSizeInBits + shift) << 16); in NEONShiftLeftImmediate()
1980 const VRegister& vn, int shift, in NEONShiftRightImmediate() argument
1982 int laneSizeInBits = vn.LaneSizeInBits(); in NEONShiftRightImmediate()
1984 NEONShiftImmediate(vd, vn, op, ((2 * laneSizeInBits) - shift) << 16); in NEONShiftRightImmediate()
1987 void Assembler::NEONShiftImmediateL(const VRegister& vd, const VRegister& vn, in NEONShiftImmediateL() argument
1989 int laneSizeInBits = vn.LaneSizeInBits(); in NEONShiftImmediateL()
1993 DCHECK((vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) || in NEONShiftImmediateL()
1994 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) || in NEONShiftImmediateL()
1995 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); in NEONShiftImmediateL()
1997 q = vn.IsD() ? 0 : NEON_Q; in NEONShiftImmediateL()
1998 Emit(q | op | immh_immb | Rn(vn) | Rd(vd)); in NEONShiftImmediateL()
2001 void Assembler::NEONShiftImmediateN(const VRegister& vd, const VRegister& vn, in NEONShiftImmediateN() argument
2008 if (vn.IsScalar()) { in NEONShiftImmediateN()
2009 DCHECK((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) || in NEONShiftImmediateN()
2010 (vd.Is1S() && vn.Is1D())); in NEONShiftImmediateN()
2014 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) || in NEONShiftImmediateN()
2015 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEONShiftImmediateN()
2016 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D())); in NEONShiftImmediateN()
2020 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd)); in NEONShiftImmediateN()
2023 void Assembler::shl(const VRegister& vd, const VRegister& vn, int shift) { in shl() argument
2025 NEONShiftLeftImmediate(vd, vn, shift, NEON_SHL); in shl()
2028 void Assembler::sli(const VRegister& vd, const VRegister& vn, int shift) { in sli() argument
2030 NEONShiftLeftImmediate(vd, vn, shift, NEON_SLI); in sli()
2033 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) { in sqshl() argument
2034 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHL_imm); in sqshl()
2037 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) { in sqshlu() argument
2038 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHLU); in sqshlu()
2041 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) { in uqshl() argument
2042 NEONShiftLeftImmediate(vd, vn, shift, NEON_UQSHL_imm); in uqshl()
2045 void Assembler::sshll(const VRegister& vd, const VRegister& vn, int shift) { in sshll() argument
2046 DCHECK(vn.IsD()); in sshll()
2047 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL); in sshll()
2050 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) { in sshll2() argument
2051 DCHECK(vn.IsQ()); in sshll2()
2052 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL); in sshll2()
2055 void Assembler::sxtl(const VRegister& vd, const VRegister& vn) { in sxtl() argument
2056 sshll(vd, vn, 0); in sxtl()
2059 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) { in sxtl2() argument
2060 sshll2(vd, vn, 0); in sxtl2()
2063 void Assembler::ushll(const VRegister& vd, const VRegister& vn, int shift) { in ushll() argument
2064 DCHECK(vn.IsD()); in ushll()
2065 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL); in ushll()
2068 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) { in ushll2() argument
2069 DCHECK(vn.IsQ()); in ushll2()
2070 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL); in ushll2()
2073 void Assembler::uxtl(const VRegister& vd, const VRegister& vn) { in uxtl() argument
2074 ushll(vd, vn, 0); in uxtl()
2077 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) { in uxtl2() argument
2078 ushll2(vd, vn, 0); in uxtl2()
2081 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) { in sri() argument
2083 NEONShiftRightImmediate(vd, vn, shift, NEON_SRI); in sri()
2086 void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) { in sshr() argument
2088 NEONShiftRightImmediate(vd, vn, shift, NEON_SSHR); in sshr()
2091 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) { in ushr() argument
2093 NEONShiftRightImmediate(vd, vn, shift, NEON_USHR); in ushr()
2096 void Assembler::srshr(const VRegister& vd, const VRegister& vn, int shift) { in srshr() argument
2098 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSHR); in srshr()
2101 void Assembler::urshr(const VRegister& vd, const VRegister& vn, int shift) { in urshr() argument
2103 NEONShiftRightImmediate(vd, vn, shift, NEON_URSHR); in urshr()
2106 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) { in ssra() argument
2108 NEONShiftRightImmediate(vd, vn, shift, NEON_SSRA); in ssra()
2111 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) { in usra() argument
2113 NEONShiftRightImmediate(vd, vn, shift, NEON_USRA); in usra()
2116 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) { in srsra() argument
2118 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSRA); in srsra()
2121 void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) { in ursra() argument
2123 NEONShiftRightImmediate(vd, vn, shift, NEON_URSRA); in ursra()
2126 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) { in shrn() argument
2127 DCHECK(vn.IsVector() && vd.IsD()); in shrn()
2128 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN); in shrn()
2131 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) { in shrn2() argument
2132 DCHECK(vn.IsVector() && vd.IsQ()); in shrn2()
2133 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN); in shrn2()
2136 void Assembler::rshrn(const VRegister& vd, const VRegister& vn, int shift) { in rshrn() argument
2137 DCHECK(vn.IsVector() && vd.IsD()); in rshrn()
2138 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN); in rshrn()
2141 void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) { in rshrn2() argument
2142 DCHECK(vn.IsVector() && vd.IsQ()); in rshrn2()
2143 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN); in rshrn2()
2146 void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) { in sqshrn() argument
2147 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqshrn()
2148 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN); in sqshrn()
2151 void Assembler::sqshrn2(const VRegister& vd, const VRegister& vn, int shift) { in sqshrn2() argument
2152 DCHECK(vn.IsVector() && vd.IsQ()); in sqshrn2()
2153 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN); in sqshrn2()
2156 void Assembler::sqrshrn(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrn() argument
2157 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqrshrn()
2158 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN); in sqrshrn()
2161 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrn2() argument
2162 DCHECK(vn.IsVector() && vd.IsQ()); in sqrshrn2()
2163 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN); in sqrshrn2()
2166 void Assembler::sqshrun(const VRegister& vd, const VRegister& vn, int shift) { in sqshrun() argument
2167 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqshrun()
2168 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN); in sqshrun()
2171 void Assembler::sqshrun2(const VRegister& vd, const VRegister& vn, int shift) { in sqshrun2() argument
2172 DCHECK(vn.IsVector() && vd.IsQ()); in sqshrun2()
2173 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN); in sqshrun2()
2176 void Assembler::sqrshrun(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrun() argument
2177 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in sqrshrun()
2178 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN); in sqrshrun()
2181 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrun2() argument
2182 DCHECK(vn.IsVector() && vd.IsQ()); in sqrshrun2()
2183 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN); in sqrshrun2()
2186 void Assembler::uqshrn(const VRegister& vd, const VRegister& vn, int shift) { in uqshrn() argument
2187 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in uqshrn()
2188 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN); in uqshrn()
2191 void Assembler::uqshrn2(const VRegister& vd, const VRegister& vn, int shift) { in uqshrn2() argument
2192 DCHECK(vn.IsVector() && vd.IsQ()); in uqshrn2()
2193 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN); in uqshrn2()
2196 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) { in uqrshrn() argument
2197 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar())); in uqrshrn()
2198 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN); in uqrshrn()
2201 void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) { in uqrshrn2() argument
2202 DCHECK(vn.IsVector() && vd.IsQ()); in uqrshrn2()
2203 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN); in uqrshrn2()
2206 void Assembler::uaddw(const VRegister& vd, const VRegister& vn, in uaddw() argument
2209 NEON3DifferentW(vd, vn, vm, NEON_UADDW); in uaddw()
2212 void Assembler::uaddw2(const VRegister& vd, const VRegister& vn, in uaddw2() argument
2215 NEON3DifferentW(vd, vn, vm, NEON_UADDW2); in uaddw2()
2218 void Assembler::saddw(const VRegister& vd, const VRegister& vn, in saddw() argument
2221 NEON3DifferentW(vd, vn, vm, NEON_SADDW); in saddw()
2224 void Assembler::saddw2(const VRegister& vd, const VRegister& vn, in saddw2() argument
2227 NEON3DifferentW(vd, vn, vm, NEON_SADDW2); in saddw2()
2230 void Assembler::usubw(const VRegister& vd, const VRegister& vn, in usubw() argument
2233 NEON3DifferentW(vd, vn, vm, NEON_USUBW); in usubw()
2236 void Assembler::usubw2(const VRegister& vd, const VRegister& vn, in usubw2() argument
2239 NEON3DifferentW(vd, vn, vm, NEON_USUBW2); in usubw2()
2242 void Assembler::ssubw(const VRegister& vd, const VRegister& vn, in ssubw() argument
2245 NEON3DifferentW(vd, vn, vm, NEON_SSUBW); in ssubw()
2248 void Assembler::ssubw2(const VRegister& vd, const VRegister& vn, in ssubw2() argument
2251 NEON3DifferentW(vd, vn, vm, NEON_SSUBW2); in ssubw2()
2295 void Assembler::mov(const Register& rd, const VRegister& vn, int vn_index) { in mov() argument
2296 DCHECK_GE(vn.SizeInBytes(), 4); in mov()
2297 umov(rd, vn, vn_index); in mov()
2300 void Assembler::smov(const Register& rd, const VRegister& vn, int vn_index) { in smov() argument
2303 int lane_size = vn.LaneSizeInBytes(); in smov()
2322 Emit(q | NEON_SMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd)); in smov()
2325 void Assembler::cls(const VRegister& vd, const VRegister& vn) { in cls() argument
2326 DCHECK(AreSameFormat(vd, vn)); in cls()
2328 Emit(VFormat(vn) | NEON_CLS | Rn(vn) | Rd(vd)); in cls()
2331 void Assembler::clz(const VRegister& vd, const VRegister& vn) { in clz() argument
2332 DCHECK(AreSameFormat(vd, vn)); in clz()
2334 Emit(VFormat(vn) | NEON_CLZ | Rn(vn) | Rd(vd)); in clz()
2337 void Assembler::cnt(const VRegister& vd, const VRegister& vn) { in cnt() argument
2338 DCHECK(AreSameFormat(vd, vn)); in cnt()
2340 Emit(VFormat(vn) | NEON_CNT | Rn(vn) | Rd(vd)); in cnt()
2343 void Assembler::rev16(const VRegister& vd, const VRegister& vn) { in rev16() argument
2344 DCHECK(AreSameFormat(vd, vn)); in rev16()
2346 Emit(VFormat(vn) | NEON_REV16 | Rn(vn) | Rd(vd)); in rev16()
2349 void Assembler::rev32(const VRegister& vd, const VRegister& vn) { in rev32() argument
2350 DCHECK(AreSameFormat(vd, vn)); in rev32()
2352 Emit(VFormat(vn) | NEON_REV32 | Rn(vn) | Rd(vd)); in rev32()
2355 void Assembler::rev64(const VRegister& vd, const VRegister& vn) { in rev64() argument
2356 DCHECK(AreSameFormat(vd, vn)); in rev64()
2358 Emit(VFormat(vn) | NEON_REV64 | Rn(vn) | Rd(vd)); in rev64()
2361 void Assembler::ursqrte(const VRegister& vd, const VRegister& vn) { in ursqrte() argument
2362 DCHECK(AreSameFormat(vd, vn)); in ursqrte()
2364 Emit(VFormat(vn) | NEON_URSQRTE | Rn(vn) | Rd(vd)); in ursqrte()
2367 void Assembler::urecpe(const VRegister& vd, const VRegister& vn) { in urecpe() argument
2368 DCHECK(AreSameFormat(vd, vn)); in urecpe()
2370 Emit(VFormat(vn) | NEON_URECPE | Rn(vn) | Rd(vd)); in urecpe()
2373 void Assembler::NEONAddlp(const VRegister& vd, const VRegister& vn, in NEONAddlp() argument
2378 DCHECK((vn.Is8B() && vd.Is4H()) || (vn.Is4H() && vd.Is2S()) || in NEONAddlp()
2379 (vn.Is2S() && vd.Is1D()) || (vn.Is16B() && vd.Is8H()) || in NEONAddlp()
2380 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D())); in NEONAddlp()
2381 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAddlp()
2384 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() argument
2385 NEONAddlp(vd, vn, NEON_SADDLP); in saddlp()
2388 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) { in uaddlp() argument
2389 NEONAddlp(vd, vn, NEON_UADDLP); in uaddlp()
2392 void Assembler::sadalp(const VRegister& vd, const VRegister& vn) { in sadalp() argument
2393 NEONAddlp(vd, vn, NEON_SADALP); in sadalp()
2396 void Assembler::uadalp(const VRegister& vd, const VRegister& vn) { in uadalp() argument
2397 NEONAddlp(vd, vn, NEON_UADALP); in uadalp()
2400 void Assembler::NEONAcrossLanesL(const VRegister& vd, const VRegister& vn, in NEONAcrossLanesL() argument
2402 DCHECK((vn.Is8B() && vd.Is1H()) || (vn.Is16B() && vd.Is1H()) || in NEONAcrossLanesL()
2403 (vn.Is4H() && vd.Is1S()) || (vn.Is8H() && vd.Is1S()) || in NEONAcrossLanesL()
2404 (vn.Is4S() && vd.Is1D())); in NEONAcrossLanesL()
2405 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAcrossLanesL()
2408 void Assembler::saddlv(const VRegister& vd, const VRegister& vn) { in saddlv() argument
2409 NEONAcrossLanesL(vd, vn, NEON_SADDLV); in saddlv()
2412 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) { in uaddlv() argument
2413 NEONAcrossLanesL(vd, vn, NEON_UADDLV); in uaddlv()
2416 void Assembler::NEONAcrossLanes(const VRegister& vd, const VRegister& vn, in NEONAcrossLanes() argument
2418 DCHECK((vn.Is8B() && vd.Is1B()) || (vn.Is16B() && vd.Is1B()) || in NEONAcrossLanes()
2419 (vn.Is4H() && vd.Is1H()) || (vn.Is8H() && vd.Is1H()) || in NEONAcrossLanes()
2420 (vn.Is4S() && vd.Is1S())); in NEONAcrossLanes()
2422 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAcrossLanes()
2424 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONAcrossLanes()
2440 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
2442 NEONAcrossLanes(vd, vn, OP); \
2451 void Assembler::umov(const Register& rd, const VRegister& vn, int vn_index) { in umov() argument
2454 int lane_size = vn.LaneSizeInBytes(); in umov()
2480 Emit(q | NEON_UMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd)); in umov()
2483 void Assembler::mov(const VRegister& vd, const VRegister& vn, int vn_index) { in mov() argument
2485 dup(vd, vn, vn_index); in mov()
2495 void Assembler::ins(const VRegister& vd, int vd_index, const VRegister& vn, in ins() argument
2497 DCHECK(AreSameFormat(vd, vn)); in ins()
2523 ImmNEON4(format, vn_index) | Rn(vn) | Rd(vd)); in ins()
2526 void Assembler::NEONTable(const VRegister& vd, const VRegister& vn, in NEONTable() argument
2529 DCHECK(vn.Is16B()); in NEONTable()
2531 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
2534 void Assembler::tbl(const VRegister& vd, const VRegister& vn, in tbl() argument
2536 NEONTable(vd, vn, vm, NEON_TBL_1v); in tbl()
2539 void Assembler::tbl(const VRegister& vd, const VRegister& vn, in tbl() argument
2542 DCHECK(AreSameFormat(vn, vn2)); in tbl()
2543 DCHECK(AreConsecutive(vn, vn2)); in tbl()
2544 NEONTable(vd, vn, vm, NEON_TBL_2v); in tbl()
2547 void Assembler::tbl(const VRegister& vd, const VRegister& vn, in tbl() argument
2552 DCHECK(AreSameFormat(vn, vn2, vn3)); in tbl()
2553 DCHECK(AreConsecutive(vn, vn2, vn3)); in tbl()
2554 NEONTable(vd, vn, vm, NEON_TBL_3v); in tbl()
2557 void Assembler::tbl(const VRegister& vd, const VRegister& vn, in tbl() argument
2563 DCHECK(AreSameFormat(vn, vn2, vn3, vn4)); in tbl()
2564 DCHECK(AreConsecutive(vn, vn2, vn3, vn4)); in tbl()
2565 NEONTable(vd, vn, vm, NEON_TBL_4v); in tbl()
2568 void Assembler::tbx(const VRegister& vd, const VRegister& vn, in tbx() argument
2570 NEONTable(vd, vn, vm, NEON_TBX_1v); in tbx()
2573 void Assembler::tbx(const VRegister& vd, const VRegister& vn, in tbx() argument
2576 DCHECK(AreSameFormat(vn, vn2)); in tbx()
2577 DCHECK(AreConsecutive(vn, vn2)); in tbx()
2578 NEONTable(vd, vn, vm, NEON_TBX_2v); in tbx()
2581 void Assembler::tbx(const VRegister& vd, const VRegister& vn, in tbx() argument
2586 DCHECK(AreSameFormat(vn, vn2, vn3)); in tbx()
2587 DCHECK(AreConsecutive(vn, vn2, vn3)); in tbx()
2588 NEONTable(vd, vn, vm, NEON_TBX_3v); in tbx()
2591 void Assembler::tbx(const VRegister& vd, const VRegister& vn, in tbx() argument
2597 DCHECK(AreSameFormat(vn, vn2, vn3, vn4)); in tbx()
2598 DCHECK(AreConsecutive(vn, vn2, vn3, vn4)); in tbx()
2599 NEONTable(vd, vn, vm, NEON_TBX_4v); in tbx()
2602 void Assembler::mov(const VRegister& vd, int vd_index, const VRegister& vn, in mov() argument
2604 ins(vd, vd_index, vn, vn_index); in mov()
3036 void Assembler::fmov(const VRegister& vd, const VRegister& vn) { in fmov() argument
3037 DCHECK_EQ(vd.SizeInBits(), vn.SizeInBits()); in fmov()
3038 Emit(FPType(vd) | FMOV | Rd(vd) | Rn(vn)); in fmov()
3047 void Assembler::fmov(const Register& rd, const VRegister& vn, int index) { in fmov() argument
3048 DCHECK((index == 1) && vn.Is1D() && rd.IsX()); in fmov()
3050 Emit(FMOV_x_d1 | Rd(rd) | Rn(vn)); in fmov()
3073 void Assembler::fnmul(const VRegister& vd, const VRegister& vn, in fnmul() argument
3075 DCHECK(AreSameSizeAndType(vd, vn, vm)); in fnmul()
3077 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in fnmul()
3107 void Assembler::NEONFPConvertToInt(const Register& rd, const VRegister& vn, in NEONFPConvertToInt() argument
3109 Emit(SF(rd) | FPType(vn) | op | Rn(vn) | Rd(rd)); in NEONFPConvertToInt()
3112 void Assembler::NEONFPConvertToInt(const VRegister& vd, const VRegister& vn, in NEONFPConvertToInt() argument
3114 if (vn.IsScalar()) { in NEONFPConvertToInt()
3115 DCHECK((vd.Is1S() && vn.Is1S()) || (vd.Is1D() && vn.Is1D())); in NEONFPConvertToInt()
3118 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd)); in NEONFPConvertToInt()
3121 void Assembler::fcvt(const VRegister& vd, const VRegister& vn) { in fcvt() argument
3124 DCHECK(vn.Is1S() || vn.Is1H()); in fcvt()
3125 op = vn.Is1S() ? FCVT_ds : FCVT_dh; in fcvt()
3127 DCHECK(vn.Is1D() || vn.Is1H()); in fcvt()
3128 op = vn.Is1D() ? FCVT_sd : FCVT_sh; in fcvt()
3131 DCHECK(vn.Is1D() || vn.Is1S()); in fcvt()
3132 op = vn.Is1D() ? FCVT_hd : FCVT_hs; in fcvt()
3134 FPDataProcessing1Source(vd, vn, op); in fcvt()
3137 void Assembler::fcvtl(const VRegister& vd, const VRegister& vn) { in fcvtl() argument
3138 DCHECK((vd.Is4S() && vn.Is4H()) || (vd.Is2D() && vn.Is2S())); in fcvtl()
3140 Emit(format | NEON_FCVTL | Rn(vn) | Rd(vd)); in fcvtl()
3143 void Assembler::fcvtl2(const VRegister& vd, const VRegister& vn) { in fcvtl2() argument
3144 DCHECK((vd.Is4S() && vn.Is8H()) || (vd.Is2D() && vn.Is4S())); in fcvtl2()
3146 Emit(NEON_Q | format | NEON_FCVTL | Rn(vn) | Rd(vd)); in fcvtl2()
3149 void Assembler::fcvtn(const VRegister& vd, const VRegister& vn) { in fcvtn() argument
3150 DCHECK((vn.Is4S() && vd.Is4H()) || (vn.Is2D() && vd.Is2S())); in fcvtn()
3151 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0; in fcvtn()
3152 Emit(format | NEON_FCVTN | Rn(vn) | Rd(vd)); in fcvtn()
3155 void Assembler::fcvtn2(const VRegister& vd, const VRegister& vn) { in fcvtn2() argument
3156 DCHECK((vn.Is4S() && vd.Is8H()) || (vn.Is2D() && vd.Is4S())); in fcvtn2()
3157 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0; in fcvtn2()
3158 Emit(NEON_Q | format | NEON_FCVTN | Rn(vn) | Rd(vd)); in fcvtn2()
3161 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) { in fcvtxn() argument
3164 DCHECK(vd.Is1S() && vn.Is1D()); in fcvtxn()
3165 Emit(format | NEON_FCVTXN_scalar | Rn(vn) | Rd(vd)); in fcvtxn()
3167 DCHECK(vd.Is2S() && vn.Is2D()); in fcvtxn()
3168 Emit(format | NEON_FCVTXN | Rn(vn) | Rd(vd)); in fcvtxn()
3172 void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) { in fcvtxn2() argument
3173 DCHECK(vd.Is4S() && vn.Is2D()); in fcvtxn2()
3175 Emit(NEON_Q | format | NEON_FCVTXN | Rn(vn) | Rd(vd)); in fcvtxn2()
3189 void Assembler::FN(const Register& rd, const VRegister& vn) { \
3190 NEONFPConvertToInt(rd, vn, SCA_OP); \
3192 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3193 NEONFPConvertToInt(vd, vn, VEC_OP); \
3198 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in NEON_FP2REGMISC_FCVT_LIST()
3201 NEONFP2RegMisc(vd, vn, NEON_SCVTF); in NEON_FP2REGMISC_FCVT_LIST()
3204 NEONShiftRightImmediate(vd, vn, fbits, NEON_SCVTF_imm); in NEON_FP2REGMISC_FCVT_LIST()
3208 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf() argument
3211 NEONFP2RegMisc(vd, vn, NEON_UCVTF); in ucvtf()
3214 NEONShiftRightImmediate(vd, vn, fbits, NEON_UCVTF_imm); in ucvtf()
3238 void Assembler::NEON3Same(const VRegister& vd, const VRegister& vn, in NEON3Same() argument
3240 DCHECK(AreSameFormat(vd, vn, vm)); in NEON3Same()
3251 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEON3Same()
3254 void Assembler::NEONFP3Same(const VRegister& vd, const VRegister& vn, in NEONFP3Same() argument
3256 DCHECK(AreSameFormat(vd, vn, vm)); in NEONFP3Same()
3257 Emit(FPFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in NEONFP3Same()
3275 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3284 NEONFP2RegMisc(vd, vn, op); \
3289 void Assembler::shll(const VRegister& vd, const VRegister& vn, int shift) { in NEON_FP2REGMISC_LIST()
3290 DCHECK((vd.Is8H() && vn.Is8B() && shift == 8) || in NEON_FP2REGMISC_LIST()
3291 (vd.Is4S() && vn.Is4H() && shift == 16) || in NEON_FP2REGMISC_LIST()
3292 (vd.Is2D() && vn.Is2S() && shift == 32)); in NEON_FP2REGMISC_LIST()
3294 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd)); in NEON_FP2REGMISC_LIST()
3297 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) { in shll2() argument
3299 DCHECK((vd.Is8H() && vn.Is16B() && shift == 8) || in shll2()
3300 (vd.Is4S() && vn.Is8H() && shift == 16) || in shll2()
3301 (vd.Is2D() && vn.Is4S() && shift == 32)); in shll2()
3302 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd)); in shll2()
3305 void Assembler::NEONFP2RegMisc(const VRegister& vd, const VRegister& vn, in NEONFP2RegMisc() argument
3307 DCHECK(AreSameFormat(vd, vn)); in NEONFP2RegMisc()
3319 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd)); in NEONFP2RegMisc()
3322 void Assembler::fcmeq(const VRegister& vd, const VRegister& vn, double value) { in fcmeq() argument
3323 NEONFP2RegMisc(vd, vn, NEON_FCMEQ_zero, value); in fcmeq()
3326 void Assembler::fcmge(const VRegister& vd, const VRegister& vn, double value) { in fcmge() argument
3327 NEONFP2RegMisc(vd, vn, NEON_FCMGE_zero, value); in fcmge()
3330 void Assembler::fcmgt(const VRegister& vd, const VRegister& vn, double value) { in fcmgt() argument
3331 NEONFP2RegMisc(vd, vn, NEON_FCMGT_zero, value); in fcmgt()
3334 void Assembler::fcmle(const VRegister& vd, const VRegister& vn, double value) { in fcmle() argument
3335 NEONFP2RegMisc(vd, vn, NEON_FCMLE_zero, value); in fcmle()
3338 void Assembler::fcmlt(const VRegister& vd, const VRegister& vn, double value) { in fcmlt() argument
3339 NEONFP2RegMisc(vd, vn, NEON_FCMLT_zero, value); in fcmlt()
3342 void Assembler::frecpx(const VRegister& vd, const VRegister& vn) { in frecpx() argument
3344 DCHECK(AreSameFormat(vd, vn)); in frecpx()
3346 Emit(FPFormat(vd) | NEON_FRECPX_scalar | Rn(vn) | Rd(vd)); in frecpx()
3349 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) { in fcvtzs() argument
3350 DCHECK(vn.Is1S() || vn.Is1D()); in fcvtzs()
3353 Emit(SF(rd) | FPType(vn) | FCVTZS | Rn(vn) | Rd(rd)); in fcvtzs()
3355 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) | in fcvtzs()
3360 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs() argument
3363 NEONFP2RegMisc(vd, vn, NEON_FCVTZS); in fcvtzs()
3366 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm); in fcvtzs()
3370 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu() argument
3371 DCHECK(vn.Is1S() || vn.Is1D()); in fcvtzu()
3374 Emit(SF(rd) | FPType(vn) | FCVTZU | Rn(vn) | Rd(rd)); in fcvtzu()
3376 Emit(SF(rd) | FPType(vn) | FCVTZU_fixed | FPScale(64 - fbits) | Rn(vn) | in fcvtzu()
3381 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu() argument
3384 NEONFP2RegMisc(vd, vn, NEON_FCVTZU); in fcvtzu()
3387 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZU_imm); in fcvtzu()
3391 void Assembler::NEONFP2RegMisc(const VRegister& vd, const VRegister& vn, in NEONFP2RegMisc() argument
3393 DCHECK(AreSameFormat(vd, vn)); in NEONFP2RegMisc()
3394 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd)); in NEONFP2RegMisc()
3397 void Assembler::NEON2RegMisc(const VRegister& vd, const VRegister& vn, in NEON2RegMisc() argument
3399 DCHECK(AreSameFormat(vd, vn)); in NEON2RegMisc()
3411 Emit(format | op | Rn(vn) | Rd(vd)); in NEON2RegMisc()
3414 void Assembler::cmeq(const VRegister& vd, const VRegister& vn, int value) { in cmeq() argument
3416 NEON2RegMisc(vd, vn, NEON_CMEQ_zero, value); in cmeq()
3419 void Assembler::cmge(const VRegister& vd, const VRegister& vn, int value) { in cmge() argument
3421 NEON2RegMisc(vd, vn, NEON_CMGE_zero, value); in cmge()
3424 void Assembler::cmgt(const VRegister& vd, const VRegister& vn, int value) { in cmgt() argument
3426 NEON2RegMisc(vd, vn, NEON_CMGT_zero, value); in cmgt()
3429 void Assembler::cmle(const VRegister& vd, const VRegister& vn, int value) { in cmle() argument
3431 NEON2RegMisc(vd, vn, NEON_CMLE_zero, value); in cmle()
3434 void Assembler::cmlt(const VRegister& vd, const VRegister& vn, int value) { in cmlt() argument
3436 NEON2RegMisc(vd, vn, NEON_CMLT_zero, value); in cmlt()
3495 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3498 NEON3Same(vd, vn, vm, OP); \
3530 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3541 NEONFP3Same(vd, vn, vm, op); \
3546 void Assembler::addp(const VRegister& vd, const VRegister& vn) { in NEON_FP3SAME_LIST_V2()
3547 DCHECK((vd.Is1D() && vn.Is2D())); in NEON_FP3SAME_LIST_V2()
3548 Emit(SFormat(vd) | NEON_ADDP_scalar | Rn(vn) | Rd(vd)); in NEON_FP3SAME_LIST_V2()
3551 void Assembler::faddp(const VRegister& vd, const VRegister& vn) { in faddp() argument
3552 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D())); in faddp()
3553 Emit(FPFormat(vd) | NEON_FADDP_scalar | Rn(vn) | Rd(vd)); in faddp()
3556 void Assembler::fmaxp(const VRegister& vd, const VRegister& vn) { in fmaxp() argument
3557 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D())); in fmaxp()
3558 Emit(FPFormat(vd) | NEON_FMAXP_scalar | Rn(vn) | Rd(vd)); in fmaxp()
3561 void Assembler::fminp(const VRegister& vd, const VRegister& vn) { in fminp() argument
3562 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D())); in fminp()
3563 Emit(FPFormat(vd) | NEON_FMINP_scalar | Rn(vn) | Rd(vd)); in fminp()
3566 void Assembler::fmaxnmp(const VRegister& vd, const VRegister& vn) { in fmaxnmp() argument
3567 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D())); in fmaxnmp()
3568 Emit(FPFormat(vd) | NEON_FMAXNMP_scalar | Rn(vn) | Rd(vd)); in fmaxnmp()
3571 void Assembler::fminnmp(const VRegister& vd, const VRegister& vn) { in fminnmp() argument
3572 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D())); in fminnmp()
3573 Emit(FPFormat(vd) | NEON_FMINNMP_scalar | Rn(vn) | Rd(vd)); in fminnmp()
3580 void Assembler::mov(const VRegister& vd, const VRegister& vn) { in mov() argument
3581 DCHECK(AreSameFormat(vd, vn)); in mov()
3583 orr(vd.V8B(), vn.V8B(), vn.V8B()); in mov()
3586 orr(vd.V16B(), vn.V16B(), vn.V16B()); in mov()
3619 void Assembler::mvn(const VRegister& vd, const VRegister& vn) { in mvn() argument
3620 DCHECK(AreSameFormat(vd, vn)); in mvn()
3622 not_(vd.V8B(), vn.V8B()); in mvn()
3625 not_(vd.V16B(), vn.V16B()); in mvn()
3639 void Assembler::NEONFPByElement(const VRegister& vd, const VRegister& vn, in NEONFPByElement() argument
3642 DCHECK(AreSameFormat(vd, vn)); in NEONFPByElement()
3655 Rn(vn) | Rd(vd)); in NEONFPByElement()
3658 void Assembler::NEONByElement(const VRegister& vd, const VRegister& vn, in NEONByElement() argument
3661 DCHECK(AreSameFormat(vd, vn)); in NEONByElement()
3672 format = SFormat(vn); in NEONByElement()
3674 format = VFormat(vn); in NEONByElement()
3676 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | in NEONByElement()
3680 void Assembler::NEONByElementL(const VRegister& vd, const VRegister& vn, in NEONByElementL() argument
3683 DCHECK((vd.Is4S() && vn.Is4H() && vm.Is1H()) || in NEONByElementL()
3684 (vd.Is4S() && vn.Is8H() && vm.Is1H()) || in NEONByElementL()
3685 (vd.Is1S() && vn.Is1H() && vm.Is1H()) || in NEONByElementL()
3686 (vd.Is2D() && vn.Is2S() && vm.Is1S()) || in NEONByElementL()
3687 (vd.Is2D() && vn.Is4S() && vm.Is1S()) || in NEONByElementL()
3688 (vd.Is1D() && vn.Is1S() && vm.Is1S())); in NEONByElementL()
3697 format = SFormat(vn); in NEONByElementL()
3699 format = VFormat(vn); in NEONByElementL()
3701 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | in NEONByElementL()
3706 V(mul, NEON_MUL_byelement, vn.IsVector()) \
3707 V(mla, NEON_MLA_byelement, vn.IsVector()) \
3708 V(mls, NEON_MLS_byelement, vn.IsVector()) \
3713 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3716 NEONByElement(vd, vn, vm, vm_index, OP); \
3728 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3730 NEONFPByElement(vd, vn, vm, vm_index, OP); \
3736 V(sqdmull, NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3737 V(sqdmull2, NEON_SQDMULL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3738 V(sqdmlal, NEON_SQDMLAL_byelement, vn.IsScalar() || vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3739 V(sqdmlal2, NEON_SQDMLAL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3740 V(sqdmlsl, NEON_SQDMLSL_byelement, vn.IsScalar() || vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3741 V(sqdmlsl2, NEON_SQDMLSL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3742 V(smull, NEON_SMULL_byelement, vn.IsVector() && vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3743 V(smull2, NEON_SMULL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3744 V(umull, NEON_UMULL_byelement, vn.IsVector() && vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3745 V(umull2, NEON_UMULL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3746 V(smlal, NEON_SMLAL_byelement, vn.IsVector() && vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3747 V(smlal2, NEON_SMLAL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3748 V(umlal, NEON_UMLAL_byelement, vn.IsVector() && vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3749 V(umlal2, NEON_UMLAL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3750 V(smlsl, NEON_SMLSL_byelement, vn.IsVector() && vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3751 V(smlsl2, NEON_SMLSL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
3752 V(umlsl, NEON_UMLSL_byelement, vn.IsVector() && vn.IsD()) \ in NEON_FPBYELEMENT_LIST()
3753 V(umlsl2, NEON_UMLSL_byelement, vn.IsVector() && vn.IsQ()) in NEON_FPBYELEMENT_LIST()
3756 void Assembler::FN(const VRegister& vd, const VRegister& vn, \ in NEON_FPBYELEMENT_LIST()
3759 NEONByElementL(vd, vn, vm, vm_index, OP); \ in NEON_FPBYELEMENT_LIST()
3764 void Assembler::suqadd(const VRegister& vd, const VRegister& vn) {
3765 NEON2RegMisc(vd, vn, NEON_SUQADD);
3768 void Assembler::usqadd(const VRegister& vd, const VRegister& vn) { in usqadd() argument
3769 NEON2RegMisc(vd, vn, NEON_USQADD); in usqadd()
3772 void Assembler::abs(const VRegister& vd, const VRegister& vn) { in abs() argument
3774 NEON2RegMisc(vd, vn, NEON_ABS); in abs()
3777 void Assembler::sqabs(const VRegister& vd, const VRegister& vn) { in sqabs() argument
3778 NEON2RegMisc(vd, vn, NEON_SQABS); in sqabs()
3781 void Assembler::neg(const VRegister& vd, const VRegister& vn) { in neg() argument
3783 NEON2RegMisc(vd, vn, NEON_NEG); in neg()
3786 void Assembler::sqneg(const VRegister& vd, const VRegister& vn) { in sqneg() argument
3787 NEON2RegMisc(vd, vn, NEON_SQNEG); in sqneg()
3790 void Assembler::NEONXtn(const VRegister& vd, const VRegister& vn, in NEONXtn() argument
3794 DCHECK((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) || in NEONXtn()
3795 (vd.Is1S() && vn.Is1D())); in NEONXtn()
3799 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) || in NEONXtn()
3800 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEONXtn()
3801 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D())); in NEONXtn()
3804 Emit(format | op | Rn(vn) | Rd(vd)); in NEONXtn()
3807 void Assembler::xtn(const VRegister& vd, const VRegister& vn) { in xtn() argument
3809 NEONXtn(vd, vn, NEON_XTN); in xtn()
3812 void Assembler::xtn2(const VRegister& vd, const VRegister& vn) { in xtn2() argument
3814 NEONXtn(vd, vn, NEON_XTN); in xtn2()
3817 void Assembler::sqxtn(const VRegister& vd, const VRegister& vn) { in sqxtn() argument
3819 NEONXtn(vd, vn, NEON_SQXTN); in sqxtn()
3822 void Assembler::sqxtn2(const VRegister& vd, const VRegister& vn) { in sqxtn2() argument
3824 NEONXtn(vd, vn, NEON_SQXTN); in sqxtn2()
3827 void Assembler::sqxtun(const VRegister& vd, const VRegister& vn) { in sqxtun() argument
3829 NEONXtn(vd, vn, NEON_SQXTUN); in sqxtun()
3832 void Assembler::sqxtun2(const VRegister& vd, const VRegister& vn) { in sqxtun2() argument
3834 NEONXtn(vd, vn, NEON_SQXTUN); in sqxtun2()
3837 void Assembler::uqxtn(const VRegister& vd, const VRegister& vn) { in uqxtn() argument
3839 NEONXtn(vd, vn, NEON_UQXTN); in uqxtn()
3842 void Assembler::uqxtn2(const VRegister& vd, const VRegister& vn) { in uqxtn2() argument
3844 NEONXtn(vd, vn, NEON_UQXTN); in uqxtn2()
3848 void Assembler::not_(const VRegister& vd, const VRegister& vn) { in not_() argument
3849 DCHECK(AreSameFormat(vd, vn)); in not_()
3851 Emit(VFormat(vd) | NEON_RBIT_NOT | Rn(vn) | Rd(vd)); in not_()
3854 void Assembler::rbit(const VRegister& vd, const VRegister& vn) { in rbit() argument
3855 DCHECK(AreSameFormat(vd, vn)); in rbit()
3857 Emit(VFormat(vn) | (1 << NEONSize_offset) | NEON_RBIT_NOT | Rn(vn) | Rd(vd)); in rbit()
3860 void Assembler::ext(const VRegister& vd, const VRegister& vn, in ext() argument
3862 DCHECK(AreSameFormat(vd, vn, vm)); in ext()
3865 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd)); in ext()
3868 void Assembler::dup(const VRegister& vd, const VRegister& vn, int vn_index) { in dup() argument
3873 int lane_size = vn.LaneSizeInBytes(); in dup()
3899 Emit(q | scalar | NEON_DUP_ELEMENT | ImmNEON5(format, vn_index) | Rn(vn) | in dup()
4192 const VRegister& vn, in FPDataProcessing1Source() argument
4194 Emit(FPType(vn) | op | Rn(vn) | Rd(vd)); in FPDataProcessing1Source()