Lines Matching refs:vt3
2742 const VRegister& vt3, const MemOperand& src) { in ld1() argument
2744 USE(vt3); in ld1()
2745 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld1()
2746 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld1()
2751 const VRegister& vt3, const VRegister& vt4, in ld1() argument
2754 USE(vt3); in ld1()
2756 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld1()
2757 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld1()
2786 const VRegister& vt3, const MemOperand& src) { in ld3() argument
2788 USE(vt3); in ld3()
2789 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld3()
2790 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld3()
2795 const VRegister& vt3, int lane, const MemOperand& src) { in ld3() argument
2797 USE(vt3); in ld3()
2798 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld3()
2799 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld3()
2804 const VRegister& vt3, const MemOperand& src) { in ld3r() argument
2806 USE(vt3); in ld3r()
2807 DCHECK(AreSameFormat(vt, vt2, vt3)); in ld3r()
2808 DCHECK(AreConsecutive(vt, vt2, vt3)); in ld3r()
2813 const VRegister& vt3, const VRegister& vt4, in ld4() argument
2816 USE(vt3); in ld4()
2818 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld4()
2819 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld4()
2824 const VRegister& vt3, const VRegister& vt4, int lane, in ld4() argument
2827 USE(vt3); in ld4()
2829 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld4()
2830 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld4()
2835 const VRegister& vt3, const VRegister& vt4, in ld4r() argument
2838 USE(vt3); in ld4r()
2840 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in ld4r()
2841 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in ld4r()
2858 const VRegister& vt3, const MemOperand& src) { in st1() argument
2860 USE(vt3); in st1()
2861 DCHECK(AreSameFormat(vt, vt2, vt3)); in st1()
2862 DCHECK(AreConsecutive(vt, vt2, vt3)); in st1()
2867 const VRegister& vt3, const VRegister& vt4, in st1() argument
2870 USE(vt3); in st1()
2872 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in st1()
2873 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in st1()
2894 const VRegister& vt3, const MemOperand& dst) { in st3() argument
2896 USE(vt3); in st3()
2897 DCHECK(AreSameFormat(vt, vt2, vt3)); in st3()
2898 DCHECK(AreConsecutive(vt, vt2, vt3)); in st3()
2903 const VRegister& vt3, int lane, const MemOperand& dst) { in st3() argument
2905 USE(vt3); in st3()
2906 DCHECK(AreSameFormat(vt, vt2, vt3)); in st3()
2907 DCHECK(AreConsecutive(vt, vt2, vt3)); in st3()
2912 const VRegister& vt3, const VRegister& vt4, in st4() argument
2915 USE(vt3); in st4()
2917 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in st4()
2918 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in st4()
2923 const VRegister& vt3, const VRegister& vt4, int lane, in st4() argument
2926 USE(vt3); in st4()
2928 DCHECK(AreSameFormat(vt, vt2, vt3, vt4)); in st4()
2929 DCHECK(AreConsecutive(vt, vt2, vt3, vt4)); in st4()