Lines Matching refs:rd
27 void TurboAssembler::And(const Register& rd, const Register& rn, in And() argument
30 DCHECK(!rd.IsZero()); in And()
31 LogicalMacro(rd, rn, operand, AND); in And()
34 void TurboAssembler::Ands(const Register& rd, const Register& rn, in Ands() argument
37 DCHECK(!rd.IsZero()); in Ands()
38 LogicalMacro(rd, rn, operand, ANDS); in Ands()
46 void TurboAssembler::Bic(const Register& rd, const Register& rn, in Bic() argument
49 DCHECK(!rd.IsZero()); in Bic()
50 LogicalMacro(rd, rn, operand, BIC); in Bic()
54 void MacroAssembler::Bics(const Register& rd, in Bics() argument
58 DCHECK(!rd.IsZero()); in Bics()
59 LogicalMacro(rd, rn, operand, BICS); in Bics()
62 void TurboAssembler::Orr(const Register& rd, const Register& rn, in Orr() argument
65 DCHECK(!rd.IsZero()); in Orr()
66 LogicalMacro(rd, rn, operand, ORR); in Orr()
69 void TurboAssembler::Orn(const Register& rd, const Register& rn, in Orn() argument
72 DCHECK(!rd.IsZero()); in Orn()
73 LogicalMacro(rd, rn, operand, ORN); in Orn()
76 void TurboAssembler::Eor(const Register& rd, const Register& rn, in Eor() argument
79 DCHECK(!rd.IsZero()); in Eor()
80 LogicalMacro(rd, rn, operand, EOR); in Eor()
83 void TurboAssembler::Eon(const Register& rd, const Register& rn, in Eon() argument
86 DCHECK(!rd.IsZero()); in Eon()
87 LogicalMacro(rd, rn, operand, EON); in Eon()
113 void TurboAssembler::Add(const Register& rd, const Register& rn, in Add() argument
118 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, SUB); in Add()
120 AddSubMacro(rd, rn, operand, LeaveFlags, ADD); in Add()
124 void TurboAssembler::Adds(const Register& rd, const Register& rn, in Adds() argument
129 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, SUB); in Adds()
131 AddSubMacro(rd, rn, operand, SetFlags, ADD); in Adds()
135 void TurboAssembler::Sub(const Register& rd, const Register& rn, in Sub() argument
140 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, ADD); in Sub()
142 AddSubMacro(rd, rn, operand, LeaveFlags, SUB); in Sub()
146 void TurboAssembler::Subs(const Register& rd, const Register& rn, in Subs() argument
151 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, ADD); in Subs()
153 AddSubMacro(rd, rn, operand, SetFlags, SUB); in Subs()
167 void TurboAssembler::Neg(const Register& rd, const Operand& operand) { in Neg() argument
169 DCHECK(!rd.IsZero()); in Neg()
171 Mov(rd, -operand.ImmediateValue()); in Neg()
173 Sub(rd, AppropriateZeroRegFor(rd), operand); in Neg()
177 void TurboAssembler::Negs(const Register& rd, const Operand& operand) { in Negs() argument
179 Subs(rd, AppropriateZeroRegFor(rd), operand); in Negs()
182 void TurboAssembler::Adc(const Register& rd, const Register& rn, in Adc() argument
185 DCHECK(!rd.IsZero()); in Adc()
186 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC); in Adc()
190 void MacroAssembler::Adcs(const Register& rd, in Adcs() argument
194 DCHECK(!rd.IsZero()); in Adcs()
195 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC); in Adcs()
199 void MacroAssembler::Sbc(const Register& rd, in Sbc() argument
203 DCHECK(!rd.IsZero()); in Sbc()
204 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC); in Sbc()
208 void MacroAssembler::Sbcs(const Register& rd, in Sbcs() argument
212 DCHECK(!rd.IsZero()); in Sbcs()
213 AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC); in Sbcs()
217 void MacroAssembler::Ngc(const Register& rd, in Ngc() argument
220 DCHECK(!rd.IsZero()); in Ngc()
221 Register zr = AppropriateZeroRegFor(rd); in Ngc()
222 Sbc(rd, zr, operand); in Ngc()
226 void MacroAssembler::Ngcs(const Register& rd, in Ngcs() argument
229 DCHECK(!rd.IsZero()); in Ngcs()
230 Register zr = AppropriateZeroRegFor(rd); in Ngcs()
231 Sbcs(rd, zr, operand); in Ngcs()
234 void TurboAssembler::Mvn(const Register& rd, uint64_t imm) { in Mvn() argument
236 DCHECK(!rd.IsZero()); in Mvn()
237 Mov(rd, ~imm); in Mvn()
274 void TurboAssembler::Asr(const Register& rd, const Register& rn,
277 DCHECK(!rd.IsZero());
278 asr(rd, rn, shift);
281 void TurboAssembler::Asr(const Register& rd, const Register& rn, in Asr() argument
284 DCHECK(!rd.IsZero()); in Asr()
285 asrv(rd, rn, rm); in Asr()
299 void TurboAssembler::Bfi(const Register& rd, const Register& rn, unsigned lsb, in Bfi() argument
302 DCHECK(!rd.IsZero()); in Bfi()
303 bfi(rd, rn, lsb, width); in Bfi()
307 void MacroAssembler::Bfxil(const Register& rd, in Bfxil() argument
312 DCHECK(!rd.IsZero()); in Bfxil()
313 bfxil(rd, rn, lsb, width); in Bfxil()
344 void MacroAssembler::Cinc(const Register& rd, in Cinc() argument
348 DCHECK(!rd.IsZero()); in Cinc()
350 cinc(rd, rn, cond); in Cinc()
354 void MacroAssembler::Cinv(const Register& rd, in Cinv() argument
358 DCHECK(!rd.IsZero()); in Cinv()
360 cinv(rd, rn, cond); in Cinv()
363 void TurboAssembler::Cls(const Register& rd, const Register& rn) { in Cls() argument
365 DCHECK(!rd.IsZero()); in Cls()
366 cls(rd, rn); in Cls()
369 void TurboAssembler::Clz(const Register& rd, const Register& rn) { in Clz() argument
371 DCHECK(!rd.IsZero()); in Clz()
372 clz(rd, rn); in Clz()
375 void TurboAssembler::Cneg(const Register& rd, const Register& rn, in Cneg() argument
378 DCHECK(!rd.IsZero()); in Cneg()
380 cneg(rd, rn, cond); in Cneg()
386 void MacroAssembler::CzeroX(const Register& rd, in CzeroX() argument
389 DCHECK(!rd.IsSP() && rd.Is64Bits()); in CzeroX()
391 csel(rd, xzr, rd, cond); in CzeroX()
397 void TurboAssembler::CmovX(const Register& rd, const Register& rn, in CmovX() argument
400 DCHECK(!rd.IsSP()); in CmovX()
401 DCHECK(rd.Is64Bits() && rn.Is64Bits()); in CmovX()
403 if (!rd.is(rn)) { in CmovX()
404 csel(rd, rn, rd, cond); in CmovX()
413 void TurboAssembler::Cset(const Register& rd, Condition cond) { in Cset() argument
415 DCHECK(!rd.IsZero()); in Cset()
417 cset(rd, cond); in Cset()
420 void TurboAssembler::Csetm(const Register& rd, Condition cond) { in Csetm() argument
422 DCHECK(!rd.IsZero()); in Csetm()
424 csetm(rd, cond); in Csetm()
427 void TurboAssembler::Csinc(const Register& rd, const Register& rn, in Csinc() argument
430 DCHECK(!rd.IsZero()); in Csinc()
432 csinc(rd, rn, rm, cond); in Csinc()
436 void MacroAssembler::Csinv(const Register& rd, in Csinv() argument
441 DCHECK(!rd.IsZero()); in Csinv()
443 csinv(rd, rn, rm, cond); in Csinv()
447 void MacroAssembler::Csneg(const Register& rd, in Csneg() argument
452 DCHECK(!rd.IsZero()); in Csneg()
454 csneg(rd, rn, rm, cond); in Csneg()
473 void MacroAssembler::Extr(const Register& rd, in Extr() argument
478 DCHECK(!rd.IsZero()); in Extr()
479 extr(rd, rn, rm, lsb); in Extr()
529 void TurboAssembler::Fcvtas(const Register& rd, const VRegister& fn) { in Fcvtas() argument
531 DCHECK(!rd.IsZero()); in Fcvtas()
532 fcvtas(rd, fn); in Fcvtas()
535 void TurboAssembler::Fcvtau(const Register& rd, const VRegister& fn) { in Fcvtau() argument
537 DCHECK(!rd.IsZero()); in Fcvtau()
538 fcvtau(rd, fn); in Fcvtau()
541 void TurboAssembler::Fcvtms(const Register& rd, const VRegister& fn) { in Fcvtms() argument
543 DCHECK(!rd.IsZero()); in Fcvtms()
544 fcvtms(rd, fn); in Fcvtms()
547 void TurboAssembler::Fcvtmu(const Register& rd, const VRegister& fn) { in Fcvtmu() argument
549 DCHECK(!rd.IsZero()); in Fcvtmu()
550 fcvtmu(rd, fn); in Fcvtmu()
553 void TurboAssembler::Fcvtns(const Register& rd, const VRegister& fn) { in Fcvtns() argument
555 DCHECK(!rd.IsZero()); in Fcvtns()
556 fcvtns(rd, fn); in Fcvtns()
559 void TurboAssembler::Fcvtnu(const Register& rd, const VRegister& fn) { in Fcvtnu() argument
561 DCHECK(!rd.IsZero()); in Fcvtnu()
562 fcvtnu(rd, fn); in Fcvtnu()
565 void TurboAssembler::Fcvtzs(const Register& rd, const VRegister& fn) { in Fcvtzs() argument
567 DCHECK(!rd.IsZero()); in Fcvtzs()
568 fcvtzs(rd, fn); in Fcvtzs()
570 void TurboAssembler::Fcvtzu(const Register& rd, const VRegister& fn) { in Fcvtzu() argument
572 DCHECK(!rd.IsZero()); in Fcvtzu()
573 fcvtzu(rd, fn); in Fcvtzu()
683 void TurboAssembler::Fmov(Register rd, VRegister fn) { in Fmov() argument
685 DCHECK(!rd.IsZero()); in Fmov()
686 fmov(rd, fn); in Fmov()
741 void TurboAssembler::Lsl(const Register& rd, const Register& rn, in Lsl() argument
744 DCHECK(!rd.IsZero()); in Lsl()
745 lsl(rd, rn, shift); in Lsl()
748 void TurboAssembler::Lsl(const Register& rd, const Register& rn, in Lsl() argument
751 DCHECK(!rd.IsZero()); in Lsl()
752 lslv(rd, rn, rm); in Lsl()
755 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() argument
758 DCHECK(!rd.IsZero()); in Lsr()
759 lsr(rd, rn, shift); in Lsr()
762 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() argument
765 DCHECK(!rd.IsZero()); in Lsr()
766 lsrv(rd, rn, rm); in Lsr()
769 void TurboAssembler::Madd(const Register& rd, const Register& rn, in Madd() argument
772 DCHECK(!rd.IsZero()); in Madd()
773 madd(rd, rn, rm, ra); in Madd()
776 void TurboAssembler::Mneg(const Register& rd, const Register& rn, in Mneg() argument
779 DCHECK(!rd.IsZero()); in Mneg()
780 mneg(rd, rn, rm); in Mneg()
783 void MacroAssembler::Movk(const Register& rd, uint64_t imm, int shift) { in Movk() argument
785 DCHECK(!rd.IsZero()); in Movk()
786 movk(rd, imm, shift); in Movk()
801 void TurboAssembler::Msub(const Register& rd, const Register& rn, in Msub() argument
804 DCHECK(!rd.IsZero()); in Msub()
805 msub(rd, rn, rm, ra); in Msub()
808 void TurboAssembler::Mul(const Register& rd, const Register& rn, in Mul() argument
811 DCHECK(!rd.IsZero()); in Mul()
812 mul(rd, rn, rm); in Mul()
815 void TurboAssembler::Rbit(const Register& rd, const Register& rn) { in Rbit() argument
817 DCHECK(!rd.IsZero()); in Rbit()
818 rbit(rd, rn); in Rbit()
821 void TurboAssembler::Rev(const Register& rd, const Register& rn) { in Rev() argument
823 DCHECK(!rd.IsZero()); in Rev()
824 rev(rd, rn); in Rev()
835 void MacroAssembler::Rev(const Register& rd, const Register& rn) { in Rev() argument
837 DCHECK(!rd.IsZero()); in Rev()
838 rev(rd, rn); in Rev()
841 void TurboAssembler::Rev16(const Register& rd, const Register& rn) { in Rev16() argument
843 DCHECK(!rd.IsZero()); in Rev16()
844 rev16(rd, rn); in Rev16()
847 void TurboAssembler::Rev32(const Register& rd, const Register& rn) { in Rev32() argument
849 DCHECK(!rd.IsZero()); in Rev32()
850 rev32(rd, rn); in Rev32()
853 void TurboAssembler::Ror(const Register& rd, const Register& rs, in Ror() argument
856 DCHECK(!rd.IsZero()); in Ror()
857 ror(rd, rs, shift); in Ror()
860 void TurboAssembler::Ror(const Register& rd, const Register& rn, in Ror() argument
863 DCHECK(!rd.IsZero()); in Ror()
864 rorv(rd, rn, rm); in Ror()
868 void MacroAssembler::Sbfiz(const Register& rd, in Sbfiz() argument
873 DCHECK(!rd.IsZero()); in Sbfiz()
874 sbfiz(rd, rn, lsb, width); in Sbfiz()
877 void TurboAssembler::Sbfx(const Register& rd, const Register& rn, unsigned lsb, in Sbfx() argument
880 DCHECK(!rd.IsZero()); in Sbfx()
881 sbfx(rd, rn, lsb, width); in Sbfx()
890 void TurboAssembler::Sdiv(const Register& rd, const Register& rn, in Sdiv() argument
893 DCHECK(!rd.IsZero()); in Sdiv()
894 sdiv(rd, rn, rm); in Sdiv()
898 void MacroAssembler::Smaddl(const Register& rd, in Smaddl() argument
903 DCHECK(!rd.IsZero()); in Smaddl()
904 smaddl(rd, rn, rm, ra); in Smaddl()
908 void MacroAssembler::Smsubl(const Register& rd, in Smsubl() argument
913 DCHECK(!rd.IsZero()); in Smsubl()
914 smsubl(rd, rn, rm, ra); in Smsubl()
917 void TurboAssembler::Smull(const Register& rd, const Register& rn, in Smull() argument
920 DCHECK(!rd.IsZero()); in Smull()
921 smull(rd, rn, rm); in Smull()
925 void MacroAssembler::Smulh(const Register& rd, in Smulh() argument
929 DCHECK(!rd.IsZero()); in Smulh()
930 smulh(rd, rn, rm); in Smulh()
933 void TurboAssembler::Umull(const Register& rd, const Register& rn, in Umull() argument
936 DCHECK(!rd.IsZero()); in Umull()
937 umaddl(rd, rn, rm, xzr); in Umull()
940 void TurboAssembler::Sxtb(const Register& rd, const Register& rn) { in Sxtb() argument
942 DCHECK(!rd.IsZero()); in Sxtb()
943 sxtb(rd, rn); in Sxtb()
946 void TurboAssembler::Sxth(const Register& rd, const Register& rn) { in Sxth() argument
948 DCHECK(!rd.IsZero()); in Sxth()
949 sxth(rd, rn); in Sxth()
952 void TurboAssembler::Sxtw(const Register& rd, const Register& rn) { in Sxtw() argument
954 DCHECK(!rd.IsZero()); in Sxtw()
955 sxtw(rd, rn); in Sxtw()
958 void TurboAssembler::Ubfiz(const Register& rd, const Register& rn, unsigned lsb, in Ubfiz() argument
961 DCHECK(!rd.IsZero()); in Ubfiz()
962 ubfiz(rd, rn, lsb, width); in Ubfiz()
965 void TurboAssembler::Ubfx(const Register& rd, const Register& rn, unsigned lsb, in Ubfx() argument
968 DCHECK(!rd.IsZero()); in Ubfx()
969 ubfx(rd, rn, lsb, width); in Ubfx()
978 void TurboAssembler::Udiv(const Register& rd, const Register& rn, in Udiv() argument
981 DCHECK(!rd.IsZero()); in Udiv()
982 udiv(rd, rn, rm); in Udiv()
986 void MacroAssembler::Umaddl(const Register& rd, in Umaddl() argument
991 DCHECK(!rd.IsZero()); in Umaddl()
992 umaddl(rd, rn, rm, ra); in Umaddl()
996 void MacroAssembler::Umsubl(const Register& rd, in Umsubl() argument
1001 DCHECK(!rd.IsZero()); in Umsubl()
1002 umsubl(rd, rn, rm, ra); in Umsubl()
1005 void TurboAssembler::Uxtb(const Register& rd, const Register& rn) { in Uxtb() argument
1007 DCHECK(!rd.IsZero()); in Uxtb()
1008 uxtb(rd, rn); in Uxtb()
1011 void TurboAssembler::Uxth(const Register& rd, const Register& rn) { in Uxth() argument
1013 DCHECK(!rd.IsZero()); in Uxth()
1014 uxth(rd, rn); in Uxth()
1017 void TurboAssembler::Uxtw(const Register& rd, const Register& rn) { in Uxtw() argument
1019 DCHECK(!rd.IsZero()); in Uxtw()
1020 uxtw(rd, rn); in Uxtw()