Lines Matching defs:src2
587 const LogicVRegister& src2, Condition cond) { in cmp()
635 const LogicVRegister& src2) { in cmptst()
647 const LogicVRegister& src2) { in add()
676 const LogicVRegister& src2) { in addp()
686 const LogicVRegister& src2) { in mla()
695 const LogicVRegister& src2) { in mls()
704 const LogicVRegister& src2) { in mul()
714 const LogicVRegister& src2, int index) { in mul()
722 const LogicVRegister& src2, int index) { in mla()
730 const LogicVRegister& src2, int index) { in mls()
738 const LogicVRegister& src2, int index) { in smull()
747 const LogicVRegister& src2, int index) { in smull2()
756 const LogicVRegister& src2, int index) { in umull()
765 const LogicVRegister& src2, int index) { in umull2()
774 const LogicVRegister& src2, int index) { in smlal()
783 const LogicVRegister& src2, int index) { in smlal2()
792 const LogicVRegister& src2, int index) { in umlal()
801 const LogicVRegister& src2, int index) { in umlal2()
810 const LogicVRegister& src2, int index) { in smlsl()
819 const LogicVRegister& src2, int index) { in smlsl2()
828 const LogicVRegister& src2, int index) { in umlsl()
837 const LogicVRegister& src2, int index) { in umlsl2()
846 const LogicVRegister& src2, int index) { in sqdmull()
855 const LogicVRegister& src2, int index) { in sqdmull2()
864 const LogicVRegister& src2, int index) { in sqdmlal()
873 const LogicVRegister& src2, int index) { in sqdmlal2()
882 const LogicVRegister& src2, int index) { in sqdmlsl()
891 const LogicVRegister& src2, int index) { in sqdmlsl2()
900 const LogicVRegister& src2, int index) { in sqdmulh()
908 const LogicVRegister& src2, int index) { in sqrdmulh()
927 const LogicVRegister& src2) { in pmul()
938 const LogicVRegister& src2) { in pmull()
951 const LogicVRegister& src2) { in pmull2()
965 const LogicVRegister& src2) { in sub()
994 const LogicVRegister& src2) { in and_()
1004 const LogicVRegister& src2) { in orr()
1014 const LogicVRegister& src2) { in orn()
1024 const LogicVRegister& src2) { in eor()
1034 const LogicVRegister& src2) { in bic()
1055 const LogicVRegister& src2) { in bif()
1069 const LogicVRegister& src2) { in bit()
1083 const LogicVRegister& src2) { in bsl()
1097 const LogicVRegister& src2, bool max) { in SMinMax()
1115 const LogicVRegister& src2) { in smax()
1121 const LogicVRegister& src2) { in smin()
1127 const LogicVRegister& src2, bool max) { in SMinMaxP()
1152 const LogicVRegister& src2) { in smaxp()
1158 const LogicVRegister& src2) { in sminp()
1247 const LogicVRegister& src2, bool max) { in UMinMax()
1265 const LogicVRegister& src2) { in umax()
1271 const LogicVRegister& src2) { in umin()
1277 const LogicVRegister& src2, bool max) { in UMinMaxP()
1302 const LogicVRegister& src2) { in umaxp()
1308 const LogicVRegister& src2) { in uminp()
1547 const LogicVRegister& src2) { in sshl()
1606 const LogicVRegister& src2) { in ushl()
1832 const LogicVRegister& src2, bool issigned) { in AbsDiff()
1850 const LogicVRegister& src2) { in saba()
1860 const LogicVRegister& src2) { in uaba()
1979 const LogicVRegister& src2, int index) { in ext()
2324 const LogicVRegister& src2) { in uaddl()
2334 const LogicVRegister& src2) { in uaddl2()
2344 const LogicVRegister& src2) { in uaddw()
2353 const LogicVRegister& src2) { in uaddw2()
2362 const LogicVRegister& src2) { in saddl()
2372 const LogicVRegister& src2) { in saddl2()
2382 const LogicVRegister& src2) { in saddw()
2391 const LogicVRegister& src2) { in saddw2()
2400 const LogicVRegister& src2) { in usubl()
2410 const LogicVRegister& src2) { in usubl2()
2420 const LogicVRegister& src2) { in usubw()
2429 const LogicVRegister& src2) { in usubw2()
2438 const LogicVRegister& src2) { in ssubl()
2448 const LogicVRegister& src2) { in ssubl2()
2458 const LogicVRegister& src2) { in ssubw()
2467 const LogicVRegister& src2) { in ssubw2()
2476 const LogicVRegister& src2) { in uabal()
2486 const LogicVRegister& src2) { in uabal2()
2496 const LogicVRegister& src2) { in sabal()
2506 const LogicVRegister& src2) { in sabal2()
2516 const LogicVRegister& src2) { in uabdl()
2526 const LogicVRegister& src2) { in uabdl2()
2536 const LogicVRegister& src2) { in sabdl()
2546 const LogicVRegister& src2) { in sabdl2()
2556 const LogicVRegister& src2) { in umull()
2566 const LogicVRegister& src2) { in umull2()
2576 const LogicVRegister& src2) { in smull()
2586 const LogicVRegister& src2) { in smull2()
2596 const LogicVRegister& src2) { in umlsl()
2606 const LogicVRegister& src2) { in umlsl2()
2616 const LogicVRegister& src2) { in smlsl()
2626 const LogicVRegister& src2) { in smlsl2()
2636 const LogicVRegister& src2) { in umlal()
2646 const LogicVRegister& src2) { in umlal2()
2656 const LogicVRegister& src2) { in smlal()
2666 const LogicVRegister& src2) { in smlal2()
2676 const LogicVRegister& src2) { in sqdmlal()
2684 const LogicVRegister& src2) { in sqdmlal2()
2692 const LogicVRegister& src2) { in sqdmlsl()
2700 const LogicVRegister& src2) { in sqdmlsl2()
2708 const LogicVRegister& src2) { in sqdmull()
2716 const LogicVRegister& src2) { in sqdmull2()
2724 const LogicVRegister& src2, bool round) { in sqrdmulh()
2751 const LogicVRegister& src2) { in sqdmulh()
2757 const LogicVRegister& src2) { in addhn()
2766 const LogicVRegister& src2) { in addhn2()
2775 const LogicVRegister& src2) { in raddhn()
2784 const LogicVRegister& src2) { in raddhn2()
2793 const LogicVRegister& src2) { in subhn()
2802 const LogicVRegister& src2) { in subhn2()
2811 const LogicVRegister& src2) { in rsubhn()
2820 const LogicVRegister& src2) { in rsubhn2()
2829 const LogicVRegister& src2) { in trn1()
2844 const LogicVRegister& src2) { in trn2()
2859 const LogicVRegister& src2) { in zip1()
2874 const LogicVRegister& src2) { in zip2()
2889 const LogicVRegister& src2) { in uzp1()
2906 const LogicVRegister& src2) { in uzp2()
3307 const LogicVRegister& src2) { in frecps()
3320 const LogicVRegister& src2) { in frecps()
3333 const LogicVRegister& src2) { in frsqrts()
3346 const LogicVRegister& src2) { in frsqrts()
3359 const LogicVRegister& src2, Condition cond) { in fcmp()
3394 const LogicVRegister& src2, Condition cond) { in fcmp()
3422 const LogicVRegister& src2, Condition cond) { in fabscmp()
3440 const LogicVRegister& src2) { in fmla()
3454 const LogicVRegister& src2) { in fmla()
3467 const LogicVRegister& src2) { in fmls()
3481 const LogicVRegister& src2) { in fmls()
3541 const LogicVRegister& src2) { in fabd()
3627 const LogicVRegister& src2, int index) { in fmul()
3643 const LogicVRegister& src2, int index) { in fmla()
3659 const LogicVRegister& src2, int index) { in fmls()
3675 const LogicVRegister& src2, int index) { in fmulx()