2011       __ vdup(Neon16, i.OutputSimd128Register(), i.InputRegister(0));  in AssembleArchInstruction()
2035       __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));  in AssembleArchInstruction()
2052       __ vadd(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),  in AssembleArchInstruction()
2062       ASSEMBLE_NEON_PAIRWISE_OP(vpadd, Neon16);  in AssembleArchInstruction()
2065       __ vsub(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),  in AssembleArchInstruction()
2075       __ vmul(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),  in AssembleArchInstruction()
2090       __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),  in AssembleArchInstruction()
2096       __ vceq(Neon16, dst, i.InputSimd128Register(0),  in AssembleArchInstruction()
2417       __ vzip(Neon16, dst.low(), dst.high());  // dst = [0, 8, 1, 9, ... 11]  in AssembleArchInstruction()
2426       __ vzip(Neon16, dst.low(), dst.high());  // dst = [4, 12, 5, 13, ... 15]  in AssembleArchInstruction()
2437       __ vuzp(Neon16, dst, scratch);  // dst = [0, 2, 4, 6, ... 14]  in AssembleArchInstruction()
2448       __ vuzp(Neon16, scratch, dst);  // dst = [1, 3, 5, 7, ... 15]  in AssembleArchInstruction()
2459       __ vtrn(Neon16, dst, scratch);  // dst = [0, 8, 2, 10, ... 14]  in AssembleArchInstruction()
2470       __ vtrn(Neon16, scratch, dst);  // dst = [1, 9, 3, 11, ... 15]  in AssembleArchInstruction()
2576       __ vrev64(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));  in AssembleArchInstruction()
2580       __ vrev32(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));  in AssembleArchInstruction()