1895                i.InputSimd128Register(0).V16B());  in AssembleArchInstruction()
1924       __ Dup(i.OutputSimd128Register().V16B(), i.InputRegister32(0));  in AssembleArchInstruction()
1928       __ Smov(i.OutputRegister32(), i.InputSimd128Register(0).V16B(),  in AssembleArchInstruction()
1933       VRegister dst = i.OutputSimd128Register().V16B(),  in AssembleArchInstruction()
1934                 src1 = i.InputSimd128Register(0).V16B();  in AssembleArchInstruction()
1943       __ Shl(i.OutputSimd128Register().V16B(), i.InputSimd128Register(0).V16B(),  in AssembleArchInstruction()
1948       __ Sshr(i.OutputSimd128Register().V16B(),  in AssembleArchInstruction()
1949               i.InputSimd128Register(0).V16B(), i.InputInt5(1));  in AssembleArchInstruction()
1963       __ Sqxtn2(dst.V16B(), src1.V8H());  in AssembleArchInstruction()
1975       VRegister dst = i.OutputSimd128Register().V16B();  in AssembleArchInstruction()
1976       __ Cmeq(dst, i.InputSimd128Register(0).V16B(),  in AssembleArchInstruction()
1977               i.InputSimd128Register(1).V16B());  in AssembleArchInstruction()
1984       __ Ushr(i.OutputSimd128Register().V16B(),  in AssembleArchInstruction()
1985               i.InputSimd128Register(0).V16B(), i.InputInt5(1));  in AssembleArchInstruction()
1999       __ Uqxtn2(dst.V16B(), src1.V8H());  in AssembleArchInstruction()
2009       __ Movi(i.OutputSimd128Register().V16B(), 0);  in AssembleArchInstruction()
2029           __ Dup(dst.V16B(), src.V16B(), index);  in AssembleArchInstruction()
2038       VRegister dst = i.OutputSimd128Register().V16B();  in AssembleArchInstruction()
2039       DCHECK(dst.is(i.InputSimd128Register(0).V16B()));  in AssembleArchInstruction()
2040       __ Bsl(dst, i.InputSimd128Register(1).V16B(),  in AssembleArchInstruction()
2041              i.InputSimd128Register(2).V16B());  in AssembleArchInstruction()
2092       __ Ext(i.OutputSimd128Register().V16B(), i.InputSimd128Register(0).V16B(),  in AssembleArchInstruction()
2093              i.InputSimd128Register(1).V16B(), i.InputInt4(2));  in AssembleArchInstruction()
2097       Simd128Register dst = i.OutputSimd128Register().V16B(),  in AssembleArchInstruction()
2098                       src0 = i.InputSimd128Register(0).V16B(),  in AssembleArchInstruction()
2099                       src1 = i.InputSimd128Register(1).V16B();  in AssembleArchInstruction()
2118         __ Tbl(dst, src0, temp.V16B());  in AssembleArchInstruction()
2120         __ Tbl(dst, src0, src1, temp.V16B());  in AssembleArchInstruction()