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Lines Matching refs:kSimd128ScratchReg

2645           __ move_v(kSimd128ScratchReg, src0);  in AssembleArchInstruction()
2646 src0 = kSimd128ScratchReg; in AssembleArchInstruction()
2648 __ move_v(kSimd128ScratchReg, src1); in AssembleArchInstruction()
2649 src1 = kSimd128ScratchReg; in AssembleArchInstruction()
2809 __ move_v(kSimd128ScratchReg, src0); in AssembleArchInstruction()
2810 src0 = kSimd128ScratchReg; in AssembleArchInstruction()
2812 __ move_v(kSimd128ScratchReg, src1); in AssembleArchInstruction()
2813 src1 = kSimd128ScratchReg; in AssembleArchInstruction()
2833 __ shf_w(kSimd128ScratchReg, i.InputSimd128Register(0), 0xB1); in AssembleArchInstruction()
2834 __ shf_b(i.OutputSimd128Register(), kSimd128ScratchReg, 0x1B); in AssembleArchInstruction()
2855 __ ilvr_h(kSimd128ScratchReg, src, src); in AssembleArchInstruction()
2856 __ slli_w(dst, kSimd128ScratchReg, 16); in AssembleArchInstruction()
2864 __ ilvl_h(kSimd128ScratchReg, src, src); in AssembleArchInstruction()
2865 __ slli_w(dst, kSimd128ScratchReg, 16); in AssembleArchInstruction()
2887 __ ilvr_b(kSimd128ScratchReg, src, src); in AssembleArchInstruction()
2888 __ slli_h(dst, kSimd128ScratchReg, 8); in AssembleArchInstruction()
2896 __ ilvl_b(kSimd128ScratchReg, src, src); in AssembleArchInstruction()
2897 __ slli_h(dst, kSimd128ScratchReg, 8); in AssembleArchInstruction()
2906 __ sat_s_w(kSimd128ScratchReg, src0, 15); in AssembleArchInstruction()
2908 __ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg); in AssembleArchInstruction()
2916 __ sat_u_w(kSimd128ScratchReg, src0, 15); in AssembleArchInstruction()
2918 __ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg); in AssembleArchInstruction()
2940 __ sat_s_h(kSimd128ScratchReg, src0, 7); in AssembleArchInstruction()
2942 __ pckev_b(dst, kSimd128RegZero, kSimd128ScratchReg); in AssembleArchInstruction()
2950 __ sat_u_h(kSimd128ScratchReg, src0, 7); in AssembleArchInstruction()
2952 __ pckev_b(dst, kSimd128RegZero, kSimd128ScratchReg); in AssembleArchInstruction()
2960 __ shf_w(kSimd128ScratchReg, src0, 0xB1); // 2 3 0 1 : 10110001 : 0xB1 in AssembleArchInstruction()
2962 __ fadd_w(kSimd128ScratchReg, kSimd128ScratchReg, src0); in AssembleArchInstruction()
2964 __ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg); in AssembleArchInstruction()
2972 __ hadd_s_d(kSimd128ScratchReg, src0, src0); in AssembleArchInstruction()
2974 __ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg); in AssembleArchInstruction()
2982 __ hadd_s_w(kSimd128ScratchReg, src0, src0); in AssembleArchInstruction()
2984 __ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg); in AssembleArchInstruction()
3695 MSARegister temp = kSimd128ScratchReg; in AssembleMove()
3750 MSARegister temp = kSimd128ScratchReg; in AssembleSwap()
3794 MSARegister temp_1 = kSimd128ScratchReg; in AssembleSwap()