Lines Matching refs:V
14 #define TARGET_ARCH_OPCODE_LIST(V) \ argument
15 V(Mips64Add) \
16 V(Mips64Dadd) \
17 V(Mips64DaddOvf) \
18 V(Mips64Sub) \
19 V(Mips64Dsub) \
20 V(Mips64DsubOvf) \
21 V(Mips64Mul) \
22 V(Mips64MulOvf) \
23 V(Mips64MulHigh) \
24 V(Mips64DMulHigh) \
25 V(Mips64MulHighU) \
26 V(Mips64Dmul) \
27 V(Mips64Div) \
28 V(Mips64Ddiv) \
29 V(Mips64DivU) \
30 V(Mips64DdivU) \
31 V(Mips64Mod) \
32 V(Mips64Dmod) \
33 V(Mips64ModU) \
34 V(Mips64DmodU) \
35 V(Mips64And) \
36 V(Mips64And32) \
37 V(Mips64Or) \
38 V(Mips64Or32) \
39 V(Mips64Nor) \
40 V(Mips64Nor32) \
41 V(Mips64Xor) \
42 V(Mips64Xor32) \
43 V(Mips64Clz) \
44 V(Mips64Lsa) \
45 V(Mips64Dlsa) \
46 V(Mips64Shl) \
47 V(Mips64Shr) \
48 V(Mips64Sar) \
49 V(Mips64Ext) \
50 V(Mips64Ins) \
51 V(Mips64Dext) \
52 V(Mips64Dins) \
53 V(Mips64Dclz) \
54 V(Mips64Ctz) \
55 V(Mips64Dctz) \
56 V(Mips64Popcnt) \
57 V(Mips64Dpopcnt) \
58 V(Mips64Dshl) \
59 V(Mips64Dshr) \
60 V(Mips64Dsar) \
61 V(Mips64Ror) \
62 V(Mips64Dror) \
63 V(Mips64Mov) \
64 V(Mips64Tst) \
65 V(Mips64Cmp) \
66 V(Mips64CmpS) \
67 V(Mips64AddS) \
68 V(Mips64SubS) \
69 V(Mips64MulS) \
70 V(Mips64DivS) \
71 V(Mips64ModS) \
72 V(Mips64AbsS) \
73 V(Mips64NegS) \
74 V(Mips64SqrtS) \
75 V(Mips64MaxS) \
76 V(Mips64MinS) \
77 V(Mips64CmpD) \
78 V(Mips64AddD) \
79 V(Mips64SubD) \
80 V(Mips64MulD) \
81 V(Mips64DivD) \
82 V(Mips64ModD) \
83 V(Mips64AbsD) \
84 V(Mips64NegD) \
85 V(Mips64SqrtD) \
86 V(Mips64MaxD) \
87 V(Mips64MinD) \
88 V(Mips64Float64RoundDown) \
89 V(Mips64Float64RoundTruncate) \
90 V(Mips64Float64RoundUp) \
91 V(Mips64Float64RoundTiesEven) \
92 V(Mips64Float32RoundDown) \
93 V(Mips64Float32RoundTruncate) \
94 V(Mips64Float32RoundUp) \
95 V(Mips64Float32RoundTiesEven) \
96 V(Mips64CvtSD) \
97 V(Mips64CvtDS) \
98 V(Mips64TruncWD) \
99 V(Mips64RoundWD) \
100 V(Mips64FloorWD) \
101 V(Mips64CeilWD) \
102 V(Mips64TruncWS) \
103 V(Mips64RoundWS) \
104 V(Mips64FloorWS) \
105 V(Mips64CeilWS) \
106 V(Mips64TruncLS) \
107 V(Mips64TruncLD) \
108 V(Mips64TruncUwD) \
109 V(Mips64TruncUwS) \
110 V(Mips64TruncUlS) \
111 V(Mips64TruncUlD) \
112 V(Mips64CvtDW) \
113 V(Mips64CvtSL) \
114 V(Mips64CvtSW) \
115 V(Mips64CvtSUw) \
116 V(Mips64CvtSUl) \
117 V(Mips64CvtDL) \
118 V(Mips64CvtDUw) \
119 V(Mips64CvtDUl) \
120 V(Mips64Lb) \
121 V(Mips64Lbu) \
122 V(Mips64Sb) \
123 V(Mips64Lh) \
124 V(Mips64Ulh) \
125 V(Mips64Lhu) \
126 V(Mips64Ulhu) \
127 V(Mips64Sh) \
128 V(Mips64Ush) \
129 V(Mips64Ld) \
130 V(Mips64Uld) \
131 V(Mips64Lw) \
132 V(Mips64Ulw) \
133 V(Mips64Lwu) \
134 V(Mips64Ulwu) \
135 V(Mips64Sw) \
136 V(Mips64Usw) \
137 V(Mips64Sd) \
138 V(Mips64Usd) \
139 V(Mips64Lwc1) \
140 V(Mips64Ulwc1) \
141 V(Mips64Swc1) \
142 V(Mips64Uswc1) \
143 V(Mips64Ldc1) \
144 V(Mips64Uldc1) \
145 V(Mips64Sdc1) \
146 V(Mips64Usdc1) \
147 V(Mips64BitcastDL) \
148 V(Mips64BitcastLD) \
149 V(Mips64Float64ExtractLowWord32) \
150 V(Mips64Float64ExtractHighWord32) \
151 V(Mips64Float64InsertLowWord32) \
152 V(Mips64Float64InsertHighWord32) \
153 V(Mips64Float32Max) \
154 V(Mips64Float64Max) \
155 V(Mips64Float32Min) \
156 V(Mips64Float64Min) \
157 V(Mips64Float64SilenceNaN) \
158 V(Mips64Push) \
159 V(Mips64Peek) \
160 V(Mips64StoreToStackSlot) \
161 V(Mips64ByteSwap64) \
162 V(Mips64ByteSwap32) \
163 V(Mips64StackClaim) \
164 V(Mips64Seb) \
165 V(Mips64Seh) \
166 V(Mips64AssertEqual) \
167 V(Mips64S128Zero) \
168 V(Mips64I32x4Splat) \
169 V(Mips64I32x4ExtractLane) \
170 V(Mips64I32x4ReplaceLane) \
171 V(Mips64I32x4Add) \
172 V(Mips64I32x4AddHoriz) \
173 V(Mips64I32x4Sub) \
174 V(Mips64F32x4Splat) \
175 V(Mips64F32x4ExtractLane) \
176 V(Mips64F32x4ReplaceLane) \
177 V(Mips64F32x4SConvertI32x4) \
178 V(Mips64F32x4UConvertI32x4) \
179 V(Mips64I32x4Mul) \
180 V(Mips64I32x4MaxS) \
181 V(Mips64I32x4MinS) \
182 V(Mips64I32x4Eq) \
183 V(Mips64I32x4Ne) \
184 V(Mips64I32x4Shl) \
185 V(Mips64I32x4ShrS) \
186 V(Mips64I32x4ShrU) \
187 V(Mips64I32x4MaxU) \
188 V(Mips64I32x4MinU) \
189 V(Mips64F32x4Abs) \
190 V(Mips64F32x4Neg) \
191 V(Mips64F32x4RecipApprox) \
192 V(Mips64F32x4RecipSqrtApprox) \
193 V(Mips64F32x4Add) \
194 V(Mips64F32x4AddHoriz) \
195 V(Mips64F32x4Sub) \
196 V(Mips64F32x4Mul) \
197 V(Mips64F32x4Max) \
198 V(Mips64F32x4Min) \
199 V(Mips64F32x4Eq) \
200 V(Mips64F32x4Ne) \
201 V(Mips64F32x4Lt) \
202 V(Mips64F32x4Le) \
203 V(Mips64I32x4SConvertF32x4) \
204 V(Mips64I32x4UConvertF32x4) \
205 V(Mips64I32x4Neg) \
206 V(Mips64I32x4GtS) \
207 V(Mips64I32x4GeS) \
208 V(Mips64I32x4GtU) \
209 V(Mips64I32x4GeU) \
210 V(Mips64I16x8Splat) \
211 V(Mips64I16x8ExtractLane) \
212 V(Mips64I16x8ReplaceLane) \
213 V(Mips64I16x8Neg) \
214 V(Mips64I16x8Shl) \
215 V(Mips64I16x8ShrS) \
216 V(Mips64I16x8ShrU) \
217 V(Mips64I16x8Add) \
218 V(Mips64I16x8AddSaturateS) \
219 V(Mips64I16x8AddHoriz) \
220 V(Mips64I16x8Sub) \
221 V(Mips64I16x8SubSaturateS) \
222 V(Mips64I16x8Mul) \
223 V(Mips64I16x8MaxS) \
224 V(Mips64I16x8MinS) \
225 V(Mips64I16x8Eq) \
226 V(Mips64I16x8Ne) \
227 V(Mips64I16x8GtS) \
228 V(Mips64I16x8GeS) \
229 V(Mips64I16x8AddSaturateU) \
230 V(Mips64I16x8SubSaturateU) \
231 V(Mips64I16x8MaxU) \
232 V(Mips64I16x8MinU) \
233 V(Mips64I16x8GtU) \
234 V(Mips64I16x8GeU) \
235 V(Mips64I8x16Splat) \
236 V(Mips64I8x16ExtractLane) \
237 V(Mips64I8x16ReplaceLane) \
238 V(Mips64I8x16Neg) \
239 V(Mips64I8x16Shl) \
240 V(Mips64I8x16ShrS) \
241 V(Mips64I8x16Add) \
242 V(Mips64I8x16AddSaturateS) \
243 V(Mips64I8x16Sub) \
244 V(Mips64I8x16SubSaturateS) \
245 V(Mips64I8x16Mul) \
246 V(Mips64I8x16MaxS) \
247 V(Mips64I8x16MinS) \
248 V(Mips64I8x16Eq) \
249 V(Mips64I8x16Ne) \
250 V(Mips64I8x16GtS) \
251 V(Mips64I8x16GeS) \
252 V(Mips64I8x16ShrU) \
253 V(Mips64I8x16AddSaturateU) \
254 V(Mips64I8x16SubSaturateU) \
255 V(Mips64I8x16MaxU) \
256 V(Mips64I8x16MinU) \
257 V(Mips64I8x16GtU) \
258 V(Mips64I8x16GeU) \
259 V(Mips64S128And) \
260 V(Mips64S128Or) \
261 V(Mips64S128Xor) \
262 V(Mips64S128Not) \
263 V(Mips64S128Select) \
264 V(Mips64S1x4AnyTrue) \
265 V(Mips64S1x4AllTrue) \
266 V(Mips64S1x8AnyTrue) \
267 V(Mips64S1x8AllTrue) \
268 V(Mips64S1x16AnyTrue) \
269 V(Mips64S1x16AllTrue) \
270 V(Mips64S32x4InterleaveRight) \
271 V(Mips64S32x4InterleaveLeft) \
272 V(Mips64S32x4PackEven) \
273 V(Mips64S32x4PackOdd) \
274 V(Mips64S32x4InterleaveEven) \
275 V(Mips64S32x4InterleaveOdd) \
276 V(Mips64S32x4Shuffle) \
277 V(Mips64S16x8InterleaveRight) \
278 V(Mips64S16x8InterleaveLeft) \
279 V(Mips64S16x8PackEven) \
280 V(Mips64S16x8PackOdd) \
281 V(Mips64S16x8InterleaveEven) \
282 V(Mips64S16x8InterleaveOdd) \
283 V(Mips64S16x4Reverse) \
284 V(Mips64S16x2Reverse) \
285 V(Mips64S8x16InterleaveRight) \
286 V(Mips64S8x16InterleaveLeft) \
287 V(Mips64S8x16PackEven) \
288 V(Mips64S8x16PackOdd) \
289 V(Mips64S8x16InterleaveEven) \
290 V(Mips64S8x16InterleaveOdd) \
291 V(Mips64S8x16Shuffle) \
292 V(Mips64S8x16Concat) \
293 V(Mips64S8x8Reverse) \
294 V(Mips64S8x4Reverse) \
295 V(Mips64S8x2Reverse) \
296 V(Mips64MsaLd) \
297 V(Mips64MsaSt) \
298 V(Mips64I32x4SConvertI16x8Low) \
299 V(Mips64I32x4SConvertI16x8High) \
300 V(Mips64I32x4UConvertI16x8Low) \
301 V(Mips64I32x4UConvertI16x8High) \
302 V(Mips64I16x8SConvertI8x16Low) \
303 V(Mips64I16x8SConvertI8x16High) \
304 V(Mips64I16x8SConvertI32x4) \
305 V(Mips64I16x8UConvertI32x4) \
306 V(Mips64I16x8UConvertI8x16Low) \
307 V(Mips64I16x8UConvertI8x16High) \
308 V(Mips64I8x16SConvertI16x8) \
309 V(Mips64I8x16UConvertI16x8)
325 #define TARGET_ADDRESSING_MODE_LIST(V) \ argument
326 V(MRI) /* [%r0 + K] */ \
327 V(MRR) /* [%r0 + %r1] */