362   DCHECK(!cache_state_.stack_state.empty());  in PopToRegister()
363   VarState slot = cache_state_.stack_state.back();  in PopToRegister()
364   cache_state_.stack_state.pop_back();  in PopToRegister()
369       Fill(reg, cache_state_.stack_height(), slot.type());  in PopToRegister()
373       cache_state_.dec_used(slot.reg());  in PopToRegister()
387   DCHECK_EQ(cache_state_.stack_height(), target.stack_height());  in MergeFullStackWith()
391   for (uint32_t i = 0, e = cache_state_.stack_height(); i < e; ++i) {  in MergeFullStackWith()
402   uint32_t stack_height = cache_state_.stack_height();  in MergeStackWith()
418   auto& slot = cache_state_.stack_state[index];  in Spill()
424       cache_state_.dec_used(slot.reg());  in Spill()
440   for (uint32_t i = 0, e = cache_state_.stack_height(); i < e; ++i) {  in SpillAllRegisters()
441     auto& slot = cache_state_.stack_state[i];  in SpillAllRegisters()
446   cache_state_.reset_used_registers();  in SpillAllRegisters()
459   for (uint32_t idx = 0, end = cache_state_.stack_height() - num_params;  in PrepareCall()
461     VarState& slot = cache_state_.stack_state[idx];  in PrepareCall()
486   uint32_t param_base = cache_state_.stack_height() - num_params;  in PrepareCall()
495     const VarState& slot = cache_state_.stack_state[stack_idx];  in PrepareCall()
546   auto stack_end = cache_state_.stack_state.end();  in PrepareCall()
547   cache_state_.stack_state.erase(stack_end - num_params, stack_end);  in PrepareCall()
550   cache_state_.reset_used_registers();  in PrepareCall()
576     DCHECK(!cache_state_.is_used(return_reg));  in FinishCall()
608   for (const VarState& var : cache_state_.stack_state) {  in ValidateCacheState()
619   bool valid = memcmp(register_use_count, cache_state_.register_use_count,  in ValidateCacheState()
621                used_regs == cache_state_.used_registers;  in ValidateCacheState()
627   os << "found:    used_regs " << cache_state_.used_registers << ", counts "  in ValidateCacheState()
628      << PrintCollection(cache_state_.register_use_count) << "\n";  in ValidateCacheState()
636   LiftoffRegister spill_reg = cache_state_.GetNextSpillReg(candidates, pinned);  in SpillOneRegister()
642   int remaining_uses = cache_state_.get_use_count(reg);  in SpillRegister()
644   for (uint32_t idx = cache_state_.stack_height() - 1;; --idx) {  in SpillRegister()
645     DCHECK_GT(cache_state_.stack_height(), idx);  in SpillRegister()
646     auto* slot = &cache_state_.stack_state[idx];  in SpillRegister()
651       cache_state_.dec_used(slot->reg().low());  in SpillRegister()
652       cache_state_.dec_used(slot->reg().high());  in SpillRegister()
658   cache_state_.clear_used(reg);  in SpillRegister()