739   tcase_add_test(tc_core, virgl_test_transfer_read_illegal_ctx);  in virgl_init_suite()
740   tcase_add_test(tc_core, virgl_test_transfer_write_illegal_ctx);  in virgl_init_suite()
741   tcase_add_test(tc_core, virgl_test_transfer_read_unbound_res);  in virgl_init_suite()
742   tcase_add_test(tc_core, virgl_test_transfer_write_unbound_res);  in virgl_init_suite()
743   tcase_add_test(tc_core, virgl_test_transfer_read_no_iov);  in virgl_init_suite()
744   tcase_add_test(tc_core, virgl_test_transfer_write_no_iov);  in virgl_init_suite()
745   tcase_add_test(tc_core, virgl_test_transfer_read_no_box);  in virgl_init_suite()
746   tcase_add_test(tc_core, virgl_test_transfer_write_no_box);  in virgl_init_suite()
747   tcase_add_test(tc_core, virgl_test_transfer_read_1d_bad_box);  in virgl_init_suite()
748   tcase_add_test(tc_core, virgl_test_transfer_write_1d_bad_box);  in virgl_init_suite()
749   tcase_add_test(tc_core, virgl_test_transfer_read_1d_array_bad_box);  in virgl_init_suite()
750   tcase_add_test(tc_core, virgl_test_transfer_read_3d_bad_box);  in virgl_init_suite()
751   tcase_add_test(tc_core, virgl_test_transfer_1d);  in virgl_init_suite()
752   tcase_add_test(tc_core, virgl_test_transfer_1d_bad_iov);  in virgl_init_suite()
753   tcase_add_test(tc_core, virgl_test_transfer_1d_bad_iov_offset);  in virgl_init_suite()
754   tcase_add_test(tc_core, virgl_test_transfer_1d_bad_layer_stride);  in virgl_init_suite()
755   tcase_add_test(tc_core, virgl_test_transfer_2d_bad_layer_stride);  in virgl_init_suite()
756   tcase_add_test(tc_core, virgl_test_transfer_buffer_bad_layer_stride);  in virgl_init_suite()
757   tcase_add_test(tc_core, virgl_test_transfer_2d_array_bad_layer_stride);  in virgl_init_suite()
758   tcase_add_test(tc_core, virgl_test_transfer_2d_bad_level);  in virgl_init_suite()
759   tcase_add_test(tc_core, virgl_test_transfer_2d_bad_stride);  in virgl_init_suite()