1956     Register rm = operand.GetBaseRegister();  in adc()  local
1961             rm.IsLow()) {  in adc()
1962           EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));  in adc()
1973           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in adc()
1976                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in adc()
1986                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adc()
1993     Register rm = operand.GetBaseRegister();  in adc()  local
1999           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in adc()
2002                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adc()
2044     Register rm = operand.GetBaseRegister();  in adcs()  local
2049             rm.IsLow()) {  in adcs()
2050           EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));  in adcs()
2061           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in adcs()
2064                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in adcs()
2074                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adcs()
2081     Register rm = operand.GetBaseRegister();  in adcs()  local
2087           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in adcs()
2090                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adcs()
2217     Register rm = operand.GetBaseRegister();  in add()  local
2222             rm.IsLow()) {  in add()
2224                      (rm.GetCode() << 6));  in add()
2229         if (!size.IsWide() && rd.Is(rn) && !rm.Is(sp) &&  in add()
2231               (!rd.IsPC() || !rm.IsPC())) ||  in add()
2234                      ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));  in add()
2239         if (!size.IsWide() && rd.Is(rm) && rn.Is(sp) &&  in add()
2248         if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && !rm.Is(sp)) {  in add()
2249           EmitT32_16(0x4485 | (rm.GetCode() << 3));  in add()
2260           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in add()
2263                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in add()
2270           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in add()
2272         EmitT32_32(0xeb0d0000U | (rd.GetCode() << 8) | rm.GetCode() |  in add()
2283                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in add()
2291                 (rd.GetCode() << 12) | rm.GetCode() |  in add()
2298     Register rm = operand.GetBaseRegister();  in add()  local
2304           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in add()
2307                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in add()
2331     Register rm = operand.GetBaseRegister();  in add()  local
2334       if (InITBlock() && !rm.Is(sp) &&  in add()
2336             (!rd.IsPC() || !rm.IsPC())) ||  in add()
2339                    (rm.GetCode() << 3));  in add()
2411     Register rm = operand.GetBaseRegister();  in adds()  local
2416             rm.IsLow()) {  in adds()
2418                      (rm.GetCode() << 6));  in adds()
2429           !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in adds()
2432                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in adds()
2439           !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {  in adds()
2441         EmitT32_32(0xeb1d0000U | (rd.GetCode() << 8) | rm.GetCode() |  in adds()
2452                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adds()
2460                 (rd.GetCode() << 12) | rm.GetCode() |  in adds()
2467     Register rm = operand.GetBaseRegister();  in adds()  local
2473           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in adds()
2476                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in adds()
2728     Register rm = operand.GetBaseRegister();  in and_()  local
2733             rm.IsLow()) {  in and_()
2734           EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));  in and_()
2745           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in and_()
2748                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in and_()
2758                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in and_()
2765     Register rm = operand.GetBaseRegister();  in and_()  local
2771           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in and_()
2774                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in and_()
2816     Register rm = operand.GetBaseRegister();  in ands()  local
2821             rm.IsLow()) {  in ands()
2822           EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));  in ands()
2833           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ands()
2836                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in ands()
2846                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ands()
2853     Register rm = operand.GetBaseRegister();  in ands()  local
2859           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in ands()
2862                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ands()
2874                     Register rm,  in asr()  argument
2882       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in asr()
2885         EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |  in asr()
2892           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in asr()
2894         EmitT32_32(0xea4f0020U | (rd.GetCode() << 8) | rm.GetCode() |  in asr()
2904                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in asr()
2913       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in asr()
2921           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asr()
2922         EmitT32_32(0xfa40f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in asr()
2930           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asr()
2932                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in asr()
2937   Delegate(kAsr, &Assembler::asr, cond, size, rd, rm, operand);  in asr()
2943                      Register rm,  in asrs()  argument
2951       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in asrs()
2954         EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |  in asrs()
2961           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in asrs()
2963         EmitT32_32(0xea5f0020U | (rd.GetCode() << 8) | rm.GetCode() |  in asrs()
2973                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in asrs()
2982       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in asrs()
2990           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asrs()
2991         EmitT32_32(0xfa50f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in asrs()
2999           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in asrs()
3001                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in asrs()
3006   Delegate(kAsrs, &Assembler::asrs, cond, size, rd, rm, operand);  in asrs()
3283     Register rm = operand.GetBaseRegister();  in bic()  local
3288             rm.IsLow()) {  in bic()
3289           EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));  in bic()
3300           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in bic()
3303                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in bic()
3313                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bic()
3320     Register rm = operand.GetBaseRegister();  in bic()  local
3326           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in bic()
3329                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bic()
3371     Register rm = operand.GetBaseRegister();  in bics()  local
3376             rm.IsLow()) {  in bics()
3377           EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));  in bics()
3388           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in bics()
3391                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in bics()
3401                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bics()
3408     Register rm = operand.GetBaseRegister();  in bics()  local
3414           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in bics()
3417                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in bics()
3622 void Assembler::blx(Condition cond, Register rm) {  in blx()  argument
3627     if (((!rm.IsPC() && OutsideITBlockAndAlOrLast(cond)) ||  in blx()
3629       EmitT32_16(0x4780 | (rm.GetCode() << 3));  in blx()
3635     if (cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in blx()
3636       EmitA32(0x012fff30U | (cond.GetCondition() << 28) | rm.GetCode());  in blx()
3640   Delegate(kBlx, &Assembler::blx, cond, rm);  in blx()
3643 void Assembler::bx(Condition cond, Register rm) {  in bx()  argument
3649       EmitT32_16(0x4700 | (rm.GetCode() << 3));  in bx()
3656       EmitA32(0x012fff10U | (cond.GetCondition() << 28) | rm.GetCode());  in bx()
3660   Delegate(kBx, &Assembler::bx, cond, rm);  in bx()
3663 void Assembler::bxj(Condition cond, Register rm) {  in bxj()  argument
3668     if (((!rm.IsPC() && OutsideITBlockAndAlOrLast(cond)) ||  in bxj()
3670       EmitT32_32(0xf3c08f00U | (rm.GetCode() << 16));  in bxj()
3676     if (cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in bxj()
3677       EmitA32(0x012fff20U | (cond.GetCondition() << 28) | rm.GetCode());  in bxj()
3681   Delegate(kBxj, &Assembler::bxj, cond, rm);  in bxj()
3802 void Assembler::clz(Condition cond, Register rd, Register rm) {  in clz()  argument
3807     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in clz()
3808       EmitT32_32(0xfab0f080U | (rd.GetCode() << 8) | rm.GetCode() |  in clz()
3809                  (rm.GetCode() << 16));  in clz()
3816         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in clz()
3818               rm.GetCode());  in clz()
3822   Delegate(kClz, &Assembler::clz, cond, rd, rm);  in clz()
3856     Register rm = operand.GetBaseRegister();  in cmn()  local
3860         if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {  in cmn()
3861           EmitT32_16(0x42c0 | rn.GetCode() | (rm.GetCode() << 3));  in cmn()
3872           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in cmn()
3874         EmitT32_32(0xeb100f00U | (rn.GetCode() << 16) | rm.GetCode() |  in cmn()
3885                 (rn.GetCode() << 16) | rm.GetCode() |  in cmn()
3892     Register rm = operand.GetBaseRegister();  in cmn()  local
3898           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in cmn()
3900                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in cmn()
3946     Register rm = operand.GetBaseRegister();  in cmp()  local
3950         if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {  in cmp()
3951           EmitT32_16(0x4280 | rn.GetCode() | (rm.GetCode() << 3));  in cmp()
3957             ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in cmp()
3959                      ((rn.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));  in cmp()
3970           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in cmp()
3972         EmitT32_32(0xebb00f00U | (rn.GetCode() << 16) | rm.GetCode() |  in cmp()
3983                 (rn.GetCode() << 16) | rm.GetCode() |  in cmp()
3990     Register rm = operand.GetBaseRegister();  in cmp()  local
3996           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in cmp()
3998                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in cmp()
4007 void Assembler::crc32b(Condition cond, Register rd, Register rn, Register rm) {  in crc32b()  argument
4012     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32b()
4015                  rm.GetCode());  in crc32b()
4022         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32b()
4024               (rn.GetCode() << 16) | rm.GetCode());  in crc32b()
4028   Delegate(kCrc32b, &Assembler::crc32b, cond, rd, rn, rm);  in crc32b()
4031 void Assembler::crc32cb(Condition cond, Register rd, Register rn, Register rm) {  in crc32cb()  argument
4036     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32cb()
4039                  rm.GetCode());  in crc32cb()
4046         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32cb()
4048               (rn.GetCode() << 16) | rm.GetCode());  in crc32cb()
4052   Delegate(kCrc32cb, &Assembler::crc32cb, cond, rd, rn, rm);  in crc32cb()
4055 void Assembler::crc32ch(Condition cond, Register rd, Register rn, Register rm) {  in crc32ch()  argument
4060     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32ch()
4063                  rm.GetCode());  in crc32ch()
4070         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32ch()
4072               (rn.GetCode() << 16) | rm.GetCode());  in crc32ch()
4076   Delegate(kCrc32ch, &Assembler::crc32ch, cond, rd, rn, rm);  in crc32ch()
4079 void Assembler::crc32cw(Condition cond, Register rd, Register rn, Register rm) {  in crc32cw()  argument
4084     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32cw()
4087                  rm.GetCode());  in crc32cw()
4094         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32cw()
4096               (rn.GetCode() << 16) | rm.GetCode());  in crc32cw()
4100   Delegate(kCrc32cw, &Assembler::crc32cw, cond, rd, rn, rm);  in crc32cw()
4103 void Assembler::crc32h(Condition cond, Register rd, Register rn, Register rm) {  in crc32h()  argument
4108     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32h()
4111                  rm.GetCode());  in crc32h()
4118         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32h()
4120               (rn.GetCode() << 16) | rm.GetCode());  in crc32h()
4124   Delegate(kCrc32h, &Assembler::crc32h, cond, rd, rn, rm);  in crc32h()
4127 void Assembler::crc32w(Condition cond, Register rd, Register rn, Register rm) {  in crc32w()  argument
4132     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||  in crc32w()
4135                  rm.GetCode());  in crc32w()
4142         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in crc32w()
4144               (rn.GetCode() << 16) | rm.GetCode());  in crc32w()
4148   Delegate(kCrc32w, &Assembler::crc32w, cond, rd, rn, rm);  in crc32w()
4220     Register rm = operand.GetBaseRegister();  in eor()  local
4225             rm.IsLow()) {  in eor()
4226           EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));  in eor()
4237           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in eor()
4240                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in eor()
4250                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eor()
4257     Register rm = operand.GetBaseRegister();  in eor()  local
4263           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in eor()
4266                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eor()
4308     Register rm = operand.GetBaseRegister();  in eors()  local
4313             rm.IsLow()) {  in eors()
4314           EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));  in eors()
4325           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in eors()
4328                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in eors()
4338                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eors()
4345     Register rm = operand.GetBaseRegister();  in eors()  local
4351           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in eors()
4354                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in eors()
5122     Register rm = operand.GetOffsetRegister();  in ldr()  local
5125       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldr()
5128                    (rm.GetCode() << 6));  in ldr()
5137     Register rm = operand.GetOffsetRegister();  in ldr()  local
5144           ((!rm.IsPC() && (!rt.IsPC() || OutsideITBlockAndAlOrLast(cond))) ||  in ldr()
5147                    rm.GetCode() | (amount << 4));  in ldr()
5154           (!rm.IsPC() || AllowUnpredictable())) {  in ldr()
5159                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldr()
5165           cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in ldr()
5170                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldr()
5176           (!rm.IsPC() || AllowUnpredictable())) {  in ldr()
5181                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldr()
5423     Register rm = operand.GetOffsetRegister();  in ldrb()  local
5426       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrb()
5429                    (rm.GetCode() << 6));  in ldrb()
5438     Register rm = operand.GetOffsetRegister();  in ldrb()  local
5445           (!rm.IsPC() || AllowUnpredictable())) {  in ldrb()
5447                    rm.GetCode() | (amount << 4));  in ldrb()
5454           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrb()
5459                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrb()
5466           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrb()
5471                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrb()
5477           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrb()
5482                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrb()
5689     Register rm = operand.GetOffsetRegister();  in ldrd()  local
5694           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in ldrd()
5698                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrd()
5705           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in ldrd()
5709                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrd()
5716           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in ldrd()
5720                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrd()
6054     Register rm = operand.GetOffsetRegister();  in ldrh()  local
6057       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrh()
6060                    (rm.GetCode() << 6));  in ldrh()
6067           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrh()
6070                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrh()
6076           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrh()
6079                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrh()
6085           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrh()
6088                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrh()
6097     Register rm = operand.GetOffsetRegister();  in ldrh()  local
6104           (!rm.IsPC() || AllowUnpredictable())) {  in ldrh()
6106                    rm.GetCode() | (amount << 4));  in ldrh()
6307     Register rm = operand.GetOffsetRegister();  in ldrsb()  local
6310       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrsb()
6313                    (rm.GetCode() << 6));  in ldrsb()
6320           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsb()
6323                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsb()
6329           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsb()
6332                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsb()
6338           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsb()
6341                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsb()
6350     Register rm = operand.GetOffsetRegister();  in ldrsb()  local
6357           (!rm.IsPC() || AllowUnpredictable())) {  in ldrsb()
6359                    rm.GetCode() | (amount << 4));  in ldrsb()
6560     Register rm = operand.GetOffsetRegister();  in ldrsh()  local
6563       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in ldrsh()
6566                    (rm.GetCode() << 6));  in ldrsh()
6573           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsh()
6576                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsh()
6582           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsh()
6585                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsh()
6591           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ldrsh()
6594                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in ldrsh()
6603     Register rm = operand.GetOffsetRegister();  in ldrsh()  local
6610           (!rm.IsPC() || AllowUnpredictable())) {  in ldrsh()
6612                    rm.GetCode() | (amount << 4));  in ldrsh()
6711                     Register rm,  in lsl()  argument
6719       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsl()
6721         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));  in lsl()
6727           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsl()
6728         EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in lsl()
6737                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in lsl()
6746       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsl()
6754           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsl()
6755         EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsl()
6763           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsl()
6765                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsl()
6770   Delegate(kLsl, &Assembler::lsl, cond, size, rd, rm, operand);  in lsl()
6776                      Register rm,  in lsls()  argument
6784       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsls()
6786         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));  in lsls()
6792           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsls()
6793         EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in lsls()
6802                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in lsls()
6811       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsls()
6819           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsls()
6820         EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsls()
6828           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsls()
6830                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsls()
6835   Delegate(kLsls, &Assembler::lsls, cond, size, rd, rm, operand);  in lsls()
6841                     Register rm,  in lsr()  argument
6849       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsr()
6852         EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |  in lsr()
6859           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsr()
6861         EmitT32_32(0xea4f0010U | (rd.GetCode() << 8) | rm.GetCode() |  in lsr()
6871                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in lsr()
6880       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsr()
6888           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsr()
6889         EmitT32_32(0xfa20f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsr()
6897           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsr()
6899                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsr()
6904   Delegate(kLsr, &Assembler::lsr, cond, size, rd, rm, operand);  in lsr()
6910                      Register rm,  in lsrs()  argument
6918       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&  in lsrs()
6921         EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |  in lsrs()
6928           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in lsrs()
6930         EmitT32_32(0xea5f0010U | (rd.GetCode() << 8) | rm.GetCode() |  in lsrs()
6940                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));  in lsrs()
6949       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in lsrs()
6957           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsrs()
6958         EmitT32_32(0xfa30f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in lsrs()
6966           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in lsrs()
6968                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in lsrs()
6973   Delegate(kLsrs, &Assembler::lsrs, cond, size, rd, rm, operand);  in lsrs()
6977     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in mla()  argument
6983         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mla()
6985                  rm.GetCode() | (ra.GetCode() << 12));  in mla()
6992         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mla()
6995               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in mla()
6999   Delegate(kMla, &Assembler::mla, cond, rd, rn, rm, ra);  in mla()
7003     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in mlas()  argument
7009         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mlas()
7012               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in mlas()
7016   Delegate(kMlas, &Assembler::mlas, cond, rd, rn, rm, ra);  in mlas()
7020     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in mls()  argument
7025     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mls()
7028                  rm.GetCode() | (ra.GetCode() << 12));  in mls()
7035         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in mls()
7038               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in mls()
7042   Delegate(kMls, &Assembler::mls, cond, rd, rn, rm, ra);  in mls()
7052     Register rm = operand.GetBaseRegister();  in mov()  local
7060                      ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));  in mov()
7071           shift.IsValidAmount(amount) && rm.IsLow() &&  in mov()
7075         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |  in mov()
7082           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mov()
7084         EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in mov()
7095                 (rd.GetCode() << 12) | rm.GetCode() |  in mov()
7102     Register rm = operand.GetBaseRegister();  in mov()  local
7107       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7114       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7121       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7128       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in mov()
7136           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mov()
7137         EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in mov()
7145           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mov()
7147                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in mov()
7209     Register rm = operand.GetBaseRegister();  in movs()  local
7215           shift.IsValidAmount(amount) && rm.IsLow() &&  in movs()
7218         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |  in movs()
7225           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in movs()
7227         EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in movs()
7239                 (rd.GetCode() << 12) | rm.GetCode() |  in movs()
7246     Register rm = operand.GetBaseRegister();  in movs()  local
7251       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7258       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7265       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7272       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in movs()
7280           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in movs()
7281         EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in movs()
7289           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in movs()
7291                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in movs()
7448     Condition cond, EncodingSize size, Register rd, Register rn, Register rm) {  in mul()  argument
7453     if (InITBlock() && !size.IsWide() && rd.Is(rm) && rn.IsLow() &&  in mul()
7454         rm.IsLow()) {  in mul()
7461         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mul()
7463                  rm.GetCode());  in mul()
7470         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mul()
7472               rn.GetCode() | (rm.GetCode() << 8));  in mul()
7476   Delegate(kMul, &Assembler::mul, cond, size, rd, rn, rm);  in mul()
7479 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) {  in muls()  argument
7484     if (OutsideITBlock() && rd.Is(rm) && rn.IsLow() && rm.IsLow()) {  in muls()
7492         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in muls()
7494               rn.GetCode() | (rm.GetCode() << 8));  in muls()
7498   Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm);  in muls()
7532     Register rm = operand.GetBaseRegister();  in mvn()  local
7536         if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {  in mvn()
7537           EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));  in mvn()
7548           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mvn()
7550         EmitT32_32(0xea6f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in mvn()
7561                 (rd.GetCode() << 12) | rm.GetCode() |  in mvn()
7568     Register rm = operand.GetBaseRegister();  in mvn()  local
7574           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mvn()
7576                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in mvn()
7616     Register rm = operand.GetBaseRegister();  in mvns()  local
7620         if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {  in mvns()
7621           EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));  in mvns()
7632           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in mvns()
7634         EmitT32_32(0xea7f0000U | (rd.GetCode() << 8) | rm.GetCode() |  in mvns()
7645                 (rd.GetCode() << 12) | rm.GetCode() |  in mvns()
7652     Register rm = operand.GetBaseRegister();  in mvns()  local
7658           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in mvns()
7660                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |  in mvns()
7718     Register rm = operand.GetBaseRegister();  in orn()  local
7724           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orn()
7727                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orn()
7760     Register rm = operand.GetBaseRegister();  in orns()  local
7766           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orns()
7769                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orns()
7812     Register rm = operand.GetBaseRegister();  in orr()  local
7817             rm.IsLow()) {  in orr()
7818           EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));  in orr()
7829           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orr()
7832                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orr()
7842                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orr()
7849     Register rm = operand.GetBaseRegister();  in orr()  local
7855           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in orr()
7858                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orr()
7900     Register rm = operand.GetBaseRegister();  in orrs()  local
7905             rm.IsLow()) {  in orrs()
7906           EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));  in orrs()
7917           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in orrs()
7920                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in orrs()
7930                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orrs()
7937     Register rm = operand.GetBaseRegister();  in orrs()  local
7943           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in orrs()
7946                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in orrs()
7962     Register rm = operand.GetBaseRegister();  in pkhbt()  local
7968           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhbt()
7970                    rm.GetCode() | ((amount & 0x3) << 6) |  in pkhbt()
7978           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhbt()
7980                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in pkhbt()
7996     Register rm = operand.GetBaseRegister();  in pkhtb()  local
8002           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhtb()
8005                    rm.GetCode() | ((amount_ & 0x3) << 6) |  in pkhtb()
8014           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in pkhtb()
8017                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in pkhtb()
8170     Register rm = operand.GetOffsetRegister();  in pld()  local
8177           (!rm.IsPC() || AllowUnpredictable())) {  in pld()
8178         EmitT32_32(0xf810f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pld()
8186           (!rm.IsPC() || AllowUnpredictable())) {  in pld()
8190           EmitA32(0xf750f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pld()
8197           (!rm.IsPC() || AllowUnpredictable())) {  in pld()
8200           EmitA32(0xf750f060U | (rn.GetCode() << 16) | rm.GetCode() |  in pld()
8247     Register rm = operand.GetOffsetRegister();  in pldw()  local
8254           (!rm.IsPC() || AllowUnpredictable())) {  in pldw()
8255         EmitT32_32(0xf830f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pldw()
8263           (!rm.IsPC() || AllowUnpredictable())) {  in pldw()
8267           EmitA32(0xf710f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pldw()
8274           (!rm.IsPC() || AllowUnpredictable())) {  in pldw()
8277           EmitA32(0xf710f060U | (rn.GetCode() << 16) | rm.GetCode() |  in pldw()
8350     Register rm = operand.GetOffsetRegister();  in pli()  local
8357           (!rm.IsPC() || AllowUnpredictable())) {  in pli()
8358         EmitT32_32(0xf910f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pli()
8366           (!rm.IsPC() || AllowUnpredictable())) {  in pli()
8369           EmitA32(0xf650f060U | (rn.GetCode() << 16) | rm.GetCode() |  in pli()
8376           (!rm.IsPC() || AllowUnpredictable())) {  in pli()
8380           EmitA32(0xf650f000U | (rn.GetCode() << 16) | rm.GetCode() |  in pli()
8575 void Assembler::qadd(Condition cond, Register rd, Register rm, Register rn) {  in qadd()  argument
8580     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd()
8581       EmitT32_32(0xfa80f080U | (rd.GetCode() << 8) | rm.GetCode() |  in qadd()
8589         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd()
8591               rm.GetCode() | (rn.GetCode() << 16));  in qadd()
8595   Delegate(kQadd, &Assembler::qadd, cond, rd, rm, rn);  in qadd()
8598 void Assembler::qadd16(Condition cond, Register rd, Register rn, Register rm) {  in qadd16()  argument
8603     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd16()
8605                  rm.GetCode());  in qadd16()
8612         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd16()
8614               (rn.GetCode() << 16) | rm.GetCode());  in qadd16()
8618   Delegate(kQadd16, &Assembler::qadd16, cond, rd, rn, rm);  in qadd16()
8621 void Assembler::qadd8(Condition cond, Register rd, Register rn, Register rm) {  in qadd8()  argument
8626     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd8()
8628                  rm.GetCode());  in qadd8()
8635         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qadd8()
8637               (rn.GetCode() << 16) | rm.GetCode());  in qadd8()
8641   Delegate(kQadd8, &Assembler::qadd8, cond, rd, rn, rm);  in qadd8()
8644 void Assembler::qasx(Condition cond, Register rd, Register rn, Register rm) {  in qasx()  argument
8649     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qasx()
8651                  rm.GetCode());  in qasx()
8658         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qasx()
8660               (rn.GetCode() << 16) | rm.GetCode());  in qasx()
8664   Delegate(kQasx, &Assembler::qasx, cond, rd, rn, rm);  in qasx()
8667 void Assembler::qdadd(Condition cond, Register rd, Register rm, Register rn) {  in qdadd()  argument
8672     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdadd()
8673       EmitT32_32(0xfa80f090U | (rd.GetCode() << 8) | rm.GetCode() |  in qdadd()
8681         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdadd()
8683               rm.GetCode() | (rn.GetCode() << 16));  in qdadd()
8687   Delegate(kQdadd, &Assembler::qdadd, cond, rd, rm, rn);  in qdadd()
8690 void Assembler::qdsub(Condition cond, Register rd, Register rm, Register rn) {  in qdsub()  argument
8695     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdsub()
8696       EmitT32_32(0xfa80f0b0U | (rd.GetCode() << 8) | rm.GetCode() |  in qdsub()
8704         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qdsub()
8706               rm.GetCode() | (rn.GetCode() << 16));  in qdsub()
8710   Delegate(kQdsub, &Assembler::qdsub, cond, rd, rm, rn);  in qdsub()
8713 void Assembler::qsax(Condition cond, Register rd, Register rn, Register rm) {  in qsax()  argument
8718     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsax()
8720                  rm.GetCode());  in qsax()
8727         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsax()
8729               (rn.GetCode() << 16) | rm.GetCode());  in qsax()
8733   Delegate(kQsax, &Assembler::qsax, cond, rd, rn, rm);  in qsax()
8736 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) {  in qsub()  argument
8741     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub()
8742       EmitT32_32(0xfa80f0a0U | (rd.GetCode() << 8) | rm.GetCode() |  in qsub()
8750         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub()
8752               rm.GetCode() | (rn.GetCode() << 16));  in qsub()
8756   Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn);  in qsub()
8759 void Assembler::qsub16(Condition cond, Register rd, Register rn, Register rm) {  in qsub16()  argument
8764     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub16()
8766                  rm.GetCode());  in qsub16()
8773         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub16()
8775               (rn.GetCode() << 16) | rm.GetCode());  in qsub16()
8779   Delegate(kQsub16, &Assembler::qsub16, cond, rd, rn, rm);  in qsub16()
8782 void Assembler::qsub8(Condition cond, Register rd, Register rn, Register rm) {  in qsub8()  argument
8787     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub8()
8789                  rm.GetCode());  in qsub8()
8796         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in qsub8()
8798               (rn.GetCode() << 16) | rm.GetCode());  in qsub8()
8802   Delegate(kQsub8, &Assembler::qsub8, cond, rd, rn, rm);  in qsub8()
8805 void Assembler::rbit(Condition cond, Register rd, Register rm) {  in rbit()  argument
8810     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rbit()
8811       EmitT32_32(0xfa90f0a0U | (rd.GetCode() << 8) | rm.GetCode() |  in rbit()
8812                  (rm.GetCode() << 16));  in rbit()
8819         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rbit()
8821               rm.GetCode());  in rbit()
8825   Delegate(kRbit, &Assembler::rbit, cond, rd, rm);  in rbit()
8831                     Register rm) {  in rev()  argument
8836     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in rev()
8837       EmitT32_16(0xba00 | rd.GetCode() | (rm.GetCode() << 3));  in rev()
8843         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev()
8844       EmitT32_32(0xfa90f080U | (rd.GetCode() << 8) | rm.GetCode() |  in rev()
8845                  (rm.GetCode() << 16));  in rev()
8852         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev()
8854               rm.GetCode());  in rev()
8858   Delegate(kRev, &Assembler::rev, cond, size, rd, rm);  in rev()
8864                       Register rm) {  in rev16()  argument
8869     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in rev16()
8870       EmitT32_16(0xba40 | rd.GetCode() | (rm.GetCode() << 3));  in rev16()
8876         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev16()
8877       EmitT32_32(0xfa90f090U | (rd.GetCode() << 8) | rm.GetCode() |  in rev16()
8878                  (rm.GetCode() << 16));  in rev16()
8885         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rev16()
8887               rm.GetCode());  in rev16()
8891   Delegate(kRev16, &Assembler::rev16, cond, size, rd, rm);  in rev16()
8897                       Register rm) {  in revsh()  argument
8902     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in revsh()
8903       EmitT32_16(0xbac0 | rd.GetCode() | (rm.GetCode() << 3));  in revsh()
8909         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in revsh()
8910       EmitT32_32(0xfa90f0b0U | (rd.GetCode() << 8) | rm.GetCode() |  in revsh()
8911                  (rm.GetCode() << 16));  in revsh()
8918         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in revsh()
8920               rm.GetCode());  in revsh()
8924   Delegate(kRevsh, &Assembler::revsh, cond, size, rd, rm);  in revsh()
8930                     Register rm,  in ror()  argument
8939           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ror()
8940         EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode() |  in ror()
8949                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in ror()
8958       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in ror()
8966           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in ror()
8967         EmitT32_32(0xfa60f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in ror()
8975           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in ror()
8977                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in ror()
8982   Delegate(kRor, &Assembler::ror, cond, size, rd, rm, operand);  in ror()
8988                      Register rm,  in rors()  argument
8997           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rors()
8998         EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode() |  in rors()
9007                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));  in rors()
9016       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&  in rors()
9024           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in rors()
9025         EmitT32_32(0xfa70f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |  in rors()
9033           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in rors()
9035                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));  in rors()
9040   Delegate(kRors, &Assembler::rors, cond, size, rd, rm, operand);  in rors()
9043 void Assembler::rrx(Condition cond, Register rd, Register rm) {  in rrx()  argument
9048     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rrx()
9049       EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode());  in rrx()
9057               rm.GetCode());  in rrx()
9061   Delegate(kRrx, &Assembler::rrx, cond, rd, rm);  in rrx()
9064 void Assembler::rrxs(Condition cond, Register rd, Register rm) {  in rrxs()  argument
9069     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rrxs()
9070       EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode());  in rrxs()
9078               rm.GetCode());  in rrxs()
9082   Delegate(kRrxs, &Assembler::rrxs, cond, rd, rm);  in rrxs()
9125     Register rm = operand.GetBaseRegister();  in rsb()  local
9131           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rsb()
9134                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in rsb()
9144                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsb()
9151     Register rm = operand.GetBaseRegister();  in rsb()  local
9157           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rsb()
9160                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsb()
9209     Register rm = operand.GetBaseRegister();  in rsbs()  local
9215           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in rsbs()
9218                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in rsbs()
9228                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsbs()
9235     Register rm = operand.GetBaseRegister();  in rsbs()  local
9241           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rsbs()
9244                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsbs()
9273     Register rm = operand.GetBaseRegister();  in rsc()  local
9281                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsc()
9288     Register rm = operand.GetBaseRegister();  in rsc()  local
9294           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rsc()
9297                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rsc()
9326     Register rm = operand.GetBaseRegister();  in rscs()  local
9334                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rscs()
9341     Register rm = operand.GetBaseRegister();  in rscs()  local
9347           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in rscs()
9350                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in rscs()
9359 void Assembler::sadd16(Condition cond, Register rd, Register rn, Register rm) {  in sadd16()  argument
9364     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd16()
9366                  rm.GetCode());  in sadd16()
9373         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd16()
9375               (rn.GetCode() << 16) | rm.GetCode());  in sadd16()
9379   Delegate(kSadd16, &Assembler::sadd16, cond, rd, rn, rm);  in sadd16()
9382 void Assembler::sadd8(Condition cond, Register rd, Register rn, Register rm) {  in sadd8()  argument
9387     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd8()
9389                  rm.GetCode());  in sadd8()
9396         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sadd8()
9398               (rn.GetCode() << 16) | rm.GetCode());  in sadd8()
9402   Delegate(kSadd8, &Assembler::sadd8, cond, rd, rn, rm);  in sadd8()
9405 void Assembler::sasx(Condition cond, Register rd, Register rn, Register rm) {  in sasx()  argument
9410     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sasx()
9412                  rm.GetCode());  in sasx()
9419         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sasx()
9421               (rn.GetCode() << 16) | rm.GetCode());  in sasx()
9425   Delegate(kSasx, &Assembler::sasx, cond, rd, rn, rm);  in sasx()
9461     Register rm = operand.GetBaseRegister();  in sbc()  local
9466             rm.IsLow()) {  in sbc()
9467           EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));  in sbc()
9478           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sbc()
9481                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in sbc()
9491                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbc()
9498     Register rm = operand.GetBaseRegister();  in sbc()  local
9504           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in sbc()
9507                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbc()
9549     Register rm = operand.GetBaseRegister();  in sbcs()  local
9554             rm.IsLow()) {  in sbcs()
9555           EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));  in sbcs()
9566           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sbcs()
9569                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in sbcs()
9579                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbcs()
9586     Register rm = operand.GetBaseRegister();  in sbcs()  local
9592           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in sbcs()
9595                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sbcs()
9633 void Assembler::sdiv(Condition cond, Register rd, Register rn, Register rm) {  in sdiv()  argument
9638     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sdiv()
9640                  rm.GetCode());  in sdiv()
9647         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sdiv()
9649               rn.GetCode() | (rm.GetCode() << 8));  in sdiv()
9653   Delegate(kSdiv, &Assembler::sdiv, cond, rd, rn, rm);  in sdiv()
9656 void Assembler::sel(Condition cond, Register rd, Register rn, Register rm) {  in sel()  argument
9661     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sel()
9663                  rm.GetCode());  in sel()
9670         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sel()
9672               (rn.GetCode() << 16) | rm.GetCode());  in sel()
9676   Delegate(kSel, &Assembler::sel, cond, rd, rn, rm);  in sel()
9679 void Assembler::shadd16(Condition cond, Register rd, Register rn, Register rm) {  in shadd16()  argument
9684     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd16()
9686                  rm.GetCode());  in shadd16()
9693         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd16()
9695               (rn.GetCode() << 16) | rm.GetCode());  in shadd16()
9699   Delegate(kShadd16, &Assembler::shadd16, cond, rd, rn, rm);  in shadd16()
9702 void Assembler::shadd8(Condition cond, Register rd, Register rn, Register rm) {  in shadd8()  argument
9707     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd8()
9709                  rm.GetCode());  in shadd8()
9716         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shadd8()
9718               (rn.GetCode() << 16) | rm.GetCode());  in shadd8()
9722   Delegate(kShadd8, &Assembler::shadd8, cond, rd, rn, rm);  in shadd8()
9725 void Assembler::shasx(Condition cond, Register rd, Register rn, Register rm) {  in shasx()  argument
9730     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shasx()
9732                  rm.GetCode());  in shasx()
9739         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shasx()
9741               (rn.GetCode() << 16) | rm.GetCode());  in shasx()
9745   Delegate(kShasx, &Assembler::shasx, cond, rd, rn, rm);  in shasx()
9748 void Assembler::shsax(Condition cond, Register rd, Register rn, Register rm) {  in shsax()  argument
9753     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsax()
9755                  rm.GetCode());  in shsax()
9762         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsax()
9764               (rn.GetCode() << 16) | rm.GetCode());  in shsax()
9768   Delegate(kShsax, &Assembler::shsax, cond, rd, rn, rm);  in shsax()
9771 void Assembler::shsub16(Condition cond, Register rd, Register rn, Register rm) {  in shsub16()  argument
9776     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub16()
9778                  rm.GetCode());  in shsub16()
9785         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub16()
9787               (rn.GetCode() << 16) | rm.GetCode());  in shsub16()
9791   Delegate(kShsub16, &Assembler::shsub16, cond, rd, rn, rm);  in shsub16()
9794 void Assembler::shsub8(Condition cond, Register rd, Register rn, Register rm) {  in shsub8()  argument
9799     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub8()
9801                  rm.GetCode());  in shsub8()
9808         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in shsub8()
9810               (rn.GetCode() << 16) | rm.GetCode());  in shsub8()
9814   Delegate(kShsub8, &Assembler::shsub8, cond, rd, rn, rm);  in shsub8()
9818     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlabb()  argument
9824         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlabb()
9826                  rm.GetCode() | (ra.GetCode() << 12));  in smlabb()
9833         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlabb()
9836               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlabb()
9840   Delegate(kSmlabb, &Assembler::smlabb, cond, rd, rn, rm, ra);  in smlabb()
9844     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlabt()  argument
9850         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlabt()
9852                  rm.GetCode() | (ra.GetCode() << 12));  in smlabt()
9859         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlabt()
9862               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlabt()
9866   Delegate(kSmlabt, &Assembler::smlabt, cond, rd, rn, rm, ra);  in smlabt()
9870     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlad()  argument
9876         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlad()
9878                  rm.GetCode() | (ra.GetCode() << 12));  in smlad()
9885         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlad()
9887               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlad()
9891   Delegate(kSmlad, &Assembler::smlad, cond, rd, rn, rm, ra);  in smlad()
9895     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smladx()  argument
9901         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smladx()
9903                  rm.GetCode() | (ra.GetCode() << 12));  in smladx()
9910         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smladx()
9912               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smladx()
9916   Delegate(kSmladx, &Assembler::smladx, cond, rd, rn, rm, ra);  in smladx()
9920     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlal()  argument
9925     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlal()
9928                  (rn.GetCode() << 16) | rm.GetCode());  in smlal()
9935         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlal()
9939               (rm.GetCode() << 8));  in smlal()
9943   Delegate(kSmlal, &Assembler::smlal, cond, rdlo, rdhi, rn, rm);  in smlal()
9947     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlalbb()  argument
9952     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbb()
9955                  (rn.GetCode() << 16) | rm.GetCode());  in smlalbb()
9962         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbb()
9966               (rm.GetCode() << 8));  in smlalbb()
9970   Delegate(kSmlalbb, &Assembler::smlalbb, cond, rdlo, rdhi, rn, rm);  in smlalbb()
9974     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlalbt()  argument
9979     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbt()
9982                  (rn.GetCode() << 16) | rm.GetCode());  in smlalbt()
9989         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlalbt()
9993               (rm.GetCode() << 8));  in smlalbt()
9997   Delegate(kSmlalbt, &Assembler::smlalbt, cond, rdlo, rdhi, rn, rm);  in smlalbt()
10001     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlald()  argument
10006     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlald()
10009                  (rn.GetCode() << 16) | rm.GetCode());  in smlald()
10016         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlald()
10020               (rm.GetCode() << 8));  in smlald()
10024   Delegate(kSmlald, &Assembler::smlald, cond, rdlo, rdhi, rn, rm);  in smlald()
10028     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlaldx()  argument
10033     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaldx()
10036                  (rn.GetCode() << 16) | rm.GetCode());  in smlaldx()
10043         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaldx()
10047               (rm.GetCode() << 8));  in smlaldx()
10051   Delegate(kSmlaldx, &Assembler::smlaldx, cond, rdlo, rdhi, rn, rm);  in smlaldx()
10055     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlals()  argument
10061         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlals()
10065               (rm.GetCode() << 8));  in smlals()
10069   Delegate(kSmlals, &Assembler::smlals, cond, rdlo, rdhi, rn, rm);  in smlals()
10073     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlaltb()  argument
10078     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltb()
10081                  (rn.GetCode() << 16) | rm.GetCode());  in smlaltb()
10088         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltb()
10092               (rm.GetCode() << 8));  in smlaltb()
10096   Delegate(kSmlaltb, &Assembler::smlaltb, cond, rdlo, rdhi, rn, rm);  in smlaltb()
10100     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlaltt()  argument
10105     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltt()
10108                  (rn.GetCode() << 16) | rm.GetCode());  in smlaltt()
10115         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlaltt()
10119               (rm.GetCode() << 8));  in smlaltt()
10123   Delegate(kSmlaltt, &Assembler::smlaltt, cond, rdlo, rdhi, rn, rm);  in smlaltt()
10127     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlatb()  argument
10133         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlatb()
10135                  rm.GetCode() | (ra.GetCode() << 12));  in smlatb()
10142         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlatb()
10145               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlatb()
10149   Delegate(kSmlatb, &Assembler::smlatb, cond, rd, rn, rm, ra);  in smlatb()
10153     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlatt()  argument
10159         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlatt()
10161                  rm.GetCode() | (ra.GetCode() << 12));  in smlatt()
10168         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlatt()
10171               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlatt()
10175   Delegate(kSmlatt, &Assembler::smlatt, cond, rd, rn, rm, ra);  in smlatt()
10179     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlawb()  argument
10185         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlawb()
10187                  rm.GetCode() | (ra.GetCode() << 12));  in smlawb()
10194         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlawb()
10197               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlawb()
10201   Delegate(kSmlawb, &Assembler::smlawb, cond, rd, rn, rm, ra);  in smlawb()
10205     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlawt()  argument
10211         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlawt()
10213                  rm.GetCode() | (ra.GetCode() << 12));  in smlawt()
10220         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smlawt()
10223               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlawt()
10227   Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra);  in smlawt()
10231     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlsd()  argument
10237         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsd()
10239                  rm.GetCode() | (ra.GetCode() << 12));  in smlsd()
10246         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsd()
10248               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlsd()
10252   Delegate(kSmlsd, &Assembler::smlsd, cond, rd, rn, rm, ra);  in smlsd()
10256     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smlsdx()  argument
10262         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsdx()
10264                  rm.GetCode() | (ra.GetCode() << 12));  in smlsdx()
10271         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smlsdx()
10273               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smlsdx()
10277   Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra);  in smlsdx()
10281     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlsld()  argument
10286     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsld()
10289                  (rn.GetCode() << 16) | rm.GetCode());  in smlsld()
10296         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsld()
10300               (rm.GetCode() << 8));  in smlsld()
10304   Delegate(kSmlsld, &Assembler::smlsld, cond, rdlo, rdhi, rn, rm);  in smlsld()
10308     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smlsldx()  argument
10313     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsldx()
10316                  (rn.GetCode() << 16) | rm.GetCode());  in smlsldx()
10323         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smlsldx()
10327               (rm.GetCode() << 8));  in smlsldx()
10331   Delegate(kSmlsldx, &Assembler::smlsldx, cond, rdlo, rdhi, rn, rm);  in smlsldx()
10335     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmla()  argument
10341         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmla()
10343                  rm.GetCode() | (ra.GetCode() << 12));  in smmla()
10350         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmla()
10352               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmla()
10356   Delegate(kSmmla, &Assembler::smmla, cond, rd, rn, rm, ra);  in smmla()
10360     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmlar()  argument
10366         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmlar()
10368                  rm.GetCode() | (ra.GetCode() << 12));  in smmlar()
10375         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmlar()
10377               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmlar()
10381   Delegate(kSmmlar, &Assembler::smmlar, cond, rd, rn, rm, ra);  in smmlar()
10385     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmls()  argument
10390     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmls()
10393                  rm.GetCode() | (ra.GetCode() << 12));  in smmls()
10400         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmls()
10403               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmls()
10407   Delegate(kSmmls, &Assembler::smmls, cond, rd, rn, rm, ra);  in smmls()
10411     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in smmlsr()  argument
10416     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmlsr()
10419                  rm.GetCode() | (ra.GetCode() << 12));  in smmlsr()
10426         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||  in smmlsr()
10429               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in smmlsr()
10433   Delegate(kSmmlsr, &Assembler::smmlsr, cond, rd, rn, rm, ra);  in smmlsr()
10436 void Assembler::smmul(Condition cond, Register rd, Register rn, Register rm) {  in smmul()  argument
10441     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmul()
10443                  rm.GetCode());  in smmul()
10450         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmul()
10452               rn.GetCode() | (rm.GetCode() << 8));  in smmul()
10456   Delegate(kSmmul, &Assembler::smmul, cond, rd, rn, rm);  in smmul()
10459 void Assembler::smmulr(Condition cond, Register rd, Register rn, Register rm) {  in smmulr()  argument
10464     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmulr()
10466                  rm.GetCode());  in smmulr()
10473         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smmulr()
10475               rn.GetCode() | (rm.GetCode() << 8));  in smmulr()
10479   Delegate(kSmmulr, &Assembler::smmulr, cond, rd, rn, rm);  in smmulr()
10482 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) {  in smuad()  argument
10487     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuad()
10489                  rm.GetCode());  in smuad()
10496         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuad()
10498               rn.GetCode() | (rm.GetCode() << 8));  in smuad()
10502   Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm);  in smuad()
10505 void Assembler::smuadx(Condition cond, Register rd, Register rn, Register rm) {  in smuadx()  argument
10510     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuadx()
10512                  rm.GetCode());  in smuadx()
10519         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smuadx()
10521               rn.GetCode() | (rm.GetCode() << 8));  in smuadx()
10525   Delegate(kSmuadx, &Assembler::smuadx, cond, rd, rn, rm);  in smuadx()
10528 void Assembler::smulbb(Condition cond, Register rd, Register rn, Register rm) {  in smulbb()  argument
10533     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbb()
10535                  rm.GetCode());  in smulbb()
10542         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbb()
10544               rn.GetCode() | (rm.GetCode() << 8));  in smulbb()
10548   Delegate(kSmulbb, &Assembler::smulbb, cond, rd, rn, rm);  in smulbb()
10551 void Assembler::smulbt(Condition cond, Register rd, Register rn, Register rm) {  in smulbt()  argument
10556     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbt()
10558                  rm.GetCode());  in smulbt()
10565         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulbt()
10567               rn.GetCode() | (rm.GetCode() << 8));  in smulbt()
10571   Delegate(kSmulbt, &Assembler::smulbt, cond, rd, rn, rm);  in smulbt()
10575     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smull()  argument
10580     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smull()
10583                  (rn.GetCode() << 16) | rm.GetCode());  in smull()
10590         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smull()
10594               (rm.GetCode() << 8));  in smull()
10598   Delegate(kSmull, &Assembler::smull, cond, rdlo, rdhi, rn, rm);  in smull()
10602     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in smulls()  argument
10608         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in smulls()
10612               (rm.GetCode() << 8));  in smulls()
10616   Delegate(kSmulls, &Assembler::smulls, cond, rdlo, rdhi, rn, rm);  in smulls()
10619 void Assembler::smultb(Condition cond, Register rd, Register rn, Register rm) {  in smultb()  argument
10624     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultb()
10626                  rm.GetCode());  in smultb()
10633         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultb()
10635               rn.GetCode() | (rm.GetCode() << 8));  in smultb()
10639   Delegate(kSmultb, &Assembler::smultb, cond, rd, rn, rm);  in smultb()
10642 void Assembler::smultt(Condition cond, Register rd, Register rn, Register rm) {  in smultt()  argument
10647     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultt()
10649                  rm.GetCode());  in smultt()
10656         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smultt()
10658               rn.GetCode() | (rm.GetCode() << 8));  in smultt()
10662   Delegate(kSmultt, &Assembler::smultt, cond, rd, rn, rm);  in smultt()
10665 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) {  in smulwb()  argument
10670     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwb()
10672                  rm.GetCode());  in smulwb()
10679         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwb()
10681               rn.GetCode() | (rm.GetCode() << 8));  in smulwb()
10685   Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm);  in smulwb()
10688 void Assembler::smulwt(Condition cond, Register rd, Register rn, Register rm) {  in smulwt()  argument
10693     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwt()
10695                  rm.GetCode());  in smulwt()
10702         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smulwt()
10704               rn.GetCode() | (rm.GetCode() << 8));  in smulwt()
10708   Delegate(kSmulwt, &Assembler::smulwt, cond, rd, rn, rm);  in smulwt()
10711 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) {  in smusd()  argument
10716     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusd()
10718                  rm.GetCode());  in smusd()
10725         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusd()
10727               rn.GetCode() | (rm.GetCode() << 8));  in smusd()
10731   Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm);  in smusd()
10734 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) {  in smusdx()  argument
10739     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusdx()
10741                  rm.GetCode());  in smusdx()
10748         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in smusdx()
10750               rn.GetCode() | (rm.GetCode() << 8));  in smusdx()
10754   Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm);  in smusdx()
10842 void Assembler::ssax(Condition cond, Register rd, Register rn, Register rm) {  in ssax()  argument
10847     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssax()
10849                  rm.GetCode());  in ssax()
10856         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssax()
10858               (rn.GetCode() << 16) | rm.GetCode());  in ssax()
10862   Delegate(kSsax, &Assembler::ssax, cond, rd, rn, rm);  in ssax()
10865 void Assembler::ssub16(Condition cond, Register rd, Register rn, Register rm) {  in ssub16()  argument
10870     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub16()
10872                  rm.GetCode());  in ssub16()
10879         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub16()
10881               (rn.GetCode() << 16) | rm.GetCode());  in ssub16()
10885   Delegate(kSsub16, &Assembler::ssub16, cond, rd, rn, rm);  in ssub16()
10888 void Assembler::ssub8(Condition cond, Register rd, Register rn, Register rm) {  in ssub8()  argument
10893     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub8()
10895                  rm.GetCode());  in ssub8()
10902         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in ssub8()
10904               (rn.GetCode() << 16) | rm.GetCode());  in ssub8()
10908   Delegate(kSsub8, &Assembler::ssub8, cond, rd, rn, rm);  in ssub8()
11442     Register rm = operand.GetOffsetRegister();  in str()  local
11445       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in str()
11448                    (rm.GetCode() << 6));  in str()
11457     Register rm = operand.GetOffsetRegister();  in str()  local
11464           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in str()
11466                    rm.GetCode() | (amount << 4));  in str()
11473           (!rm.IsPC() || AllowUnpredictable())) {  in str()
11478                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in str()
11484           cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {  in str()
11489                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in str()
11495           (!rm.IsPC() || AllowUnpredictable())) {  in str()
11500                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in str()
11603     Register rm = operand.GetOffsetRegister();  in strb()  local
11606       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in strb()
11609                    (rm.GetCode() << 6));  in strb()
11618     Register rm = operand.GetOffsetRegister();  in strb()  local
11625           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11627                    rm.GetCode() | (amount << 4));  in strb()
11634           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11639                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strb()
11646           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11651                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strb()
11657           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strb()
11662                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strb()
11756     Register rm = operand.GetOffsetRegister();  in strd()  local
11761           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in strd()
11765                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strd()
11772           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in strd()
11776                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strd()
11783           ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||  in strd()
11787                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strd()
12019     Register rm = operand.GetOffsetRegister();  in strh()  local
12022       if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&  in strh()
12025                    (rm.GetCode() << 6));  in strh()
12032           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12035                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strh()
12041           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12044                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strh()
12050           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12053                 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in strh()
12062     Register rm = operand.GetOffsetRegister();  in strh()  local
12069           ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in strh()
12071                    rm.GetCode() | (amount << 4));  in strh()
12182     Register rm = operand.GetBaseRegister();  in sub()  local
12187             rm.IsLow()) {  in sub()
12189                      (rm.GetCode() << 6));  in sub()
12194         if (rn.Is(sp) && ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sub()
12195           EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode());  in sub()
12206           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sub()
12209                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in sub()
12216           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sub()
12218         EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode() |  in sub()
12229                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sub()
12237                 (rd.GetCode() << 12) | rm.GetCode() |  in sub()
12244     Register rm = operand.GetBaseRegister();  in sub()  local
12250           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in sub()
12253                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sub()
12349     Register rm = operand.GetBaseRegister();  in subs()  local
12354             rm.IsLow()) {  in subs()
12356                      (rm.GetCode() << 6));  in subs()
12367           !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in subs()
12370                    rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |  in subs()
12377           !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {  in subs()
12379         EmitT32_32(0xebbd0000U | (rd.GetCode() << 8) | rm.GetCode() |  in subs()
12390                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in subs()
12398                 (rd.GetCode() << 12) | rm.GetCode() |  in subs()
12405     Register rm = operand.GetBaseRegister();  in subs()  local
12411           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||  in subs()
12414                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in subs()
12496     Register rm = operand.GetBaseRegister();  in sxtab()  local
12503           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab()
12506                    rm.GetCode() | (amount_ << 4));  in sxtab()
12514           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab()
12517                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sxtab()
12533     Register rm = operand.GetBaseRegister();  in sxtab16()  local
12540           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab16()
12543                    rm.GetCode() | (amount_ << 4));  in sxtab16()
12551           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtab16()
12554                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sxtab16()
12570     Register rm = operand.GetBaseRegister();  in sxtah()  local
12577           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtah()
12580                    rm.GetCode() | (amount_ << 4));  in sxtah()
12588           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtah()
12591                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in sxtah()
12607     Register rm = operand.GetBaseRegister();  in sxtb()  local
12611         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in sxtb()
12612           EmitT32_16(0xb240 | rd.GetCode() | (rm.GetCode() << 3));  in sxtb()
12624           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb()
12626         EmitT32_32(0xfa4ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in sxtb()
12635           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb()
12638                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in sxtb()
12650     Register rm = operand.GetBaseRegister();  in sxtb16()  local
12657           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb16()
12659         EmitT32_32(0xfa2ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in sxtb16()
12668           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxtb16()
12671                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in sxtb16()
12686     Register rm = operand.GetBaseRegister();  in sxth()  local
12690         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in sxth()
12691           EmitT32_16(0xb200 | rd.GetCode() | (rm.GetCode() << 3));  in sxth()
12703           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxth()
12705         EmitT32_32(0xfa0ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in sxth()
12714           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in sxth()
12717                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in sxth()
12725 void Assembler::tbb(Condition cond, Register rn, Register rm) {  in tbb()  argument
12731         (!rm.IsPC() || AllowUnpredictable())) {  in tbb()
12732       EmitT32_32(0xe8d0f000U | (rn.GetCode() << 16) | rm.GetCode());  in tbb()
12737   Delegate(kTbb, &Assembler::tbb, cond, rn, rm);  in tbb()
12740 void Assembler::tbh(Condition cond, Register rn, Register rm) {  in tbh()  argument
12746         (!rm.IsPC() || AllowUnpredictable())) {  in tbh()
12747       EmitT32_32(0xe8d0f010U | (rn.GetCode() << 16) | rm.GetCode());  in tbh()
12752   Delegate(kTbh, &Assembler::tbh, cond, rn, rm);  in tbh()
12782     Register rm = operand.GetBaseRegister();  in teq()  local
12788           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in teq()
12790         EmitT32_32(0xea900f00U | (rn.GetCode() << 16) | rm.GetCode() |  in teq()
12801                 (rn.GetCode() << 16) | rm.GetCode() |  in teq()
12808     Register rm = operand.GetBaseRegister();  in teq()  local
12814           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in teq()
12816                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in teq()
12856     Register rm = operand.GetBaseRegister();  in tst()  local
12860         if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {  in tst()
12861           EmitT32_16(0x4200 | rn.GetCode() | (rm.GetCode() << 3));  in tst()
12872           ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in tst()
12874         EmitT32_32(0xea100f00U | (rn.GetCode() << 16) | rm.GetCode() |  in tst()
12885                 (rn.GetCode() << 16) | rm.GetCode() |  in tst()
12892     Register rm = operand.GetBaseRegister();  in tst()  local
12898           ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {  in tst()
12900                 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |  in tst()
12909 void Assembler::uadd16(Condition cond, Register rd, Register rn, Register rm) {  in uadd16()  argument
12914     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd16()
12916                  rm.GetCode());  in uadd16()
12923         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd16()
12925               (rn.GetCode() << 16) | rm.GetCode());  in uadd16()
12929   Delegate(kUadd16, &Assembler::uadd16, cond, rd, rn, rm);  in uadd16()
12932 void Assembler::uadd8(Condition cond, Register rd, Register rn, Register rm) {  in uadd8()  argument
12937     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd8()
12939                  rm.GetCode());  in uadd8()
12946         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uadd8()
12948               (rn.GetCode() << 16) | rm.GetCode());  in uadd8()
12952   Delegate(kUadd8, &Assembler::uadd8, cond, rd, rn, rm);  in uadd8()
12955 void Assembler::uasx(Condition cond, Register rd, Register rn, Register rm) {  in uasx()  argument
12960     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uasx()
12962                  rm.GetCode());  in uasx()
12969         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uasx()
12971               (rn.GetCode() << 16) | rm.GetCode());  in uasx()
12975   Delegate(kUasx, &Assembler::uasx, cond, rd, rn, rm);  in uasx()
13039 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) {  in udiv()  argument
13044     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in udiv()
13046                  rm.GetCode());  in udiv()
13053         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in udiv()
13055               rn.GetCode() | (rm.GetCode() << 8));  in udiv()
13059   Delegate(kUdiv, &Assembler::udiv, cond, rd, rn, rm);  in udiv()
13062 void Assembler::uhadd16(Condition cond, Register rd, Register rn, Register rm) {  in uhadd16()  argument
13067     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd16()
13069                  rm.GetCode());  in uhadd16()
13076         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd16()
13078               (rn.GetCode() << 16) | rm.GetCode());  in uhadd16()
13082   Delegate(kUhadd16, &Assembler::uhadd16, cond, rd, rn, rm);  in uhadd16()
13085 void Assembler::uhadd8(Condition cond, Register rd, Register rn, Register rm) {  in uhadd8()  argument
13090     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd8()
13092                  rm.GetCode());  in uhadd8()
13099         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhadd8()
13101               (rn.GetCode() << 16) | rm.GetCode());  in uhadd8()
13105   Delegate(kUhadd8, &Assembler::uhadd8, cond, rd, rn, rm);  in uhadd8()
13108 void Assembler::uhasx(Condition cond, Register rd, Register rn, Register rm) {  in uhasx()  argument
13113     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhasx()
13115                  rm.GetCode());  in uhasx()
13122         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhasx()
13124               (rn.GetCode() << 16) | rm.GetCode());  in uhasx()
13128   Delegate(kUhasx, &Assembler::uhasx, cond, rd, rn, rm);  in uhasx()
13131 void Assembler::uhsax(Condition cond, Register rd, Register rn, Register rm) {  in uhsax()  argument
13136     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsax()
13138                  rm.GetCode());  in uhsax()
13145         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsax()
13147               (rn.GetCode() << 16) | rm.GetCode());  in uhsax()
13151   Delegate(kUhsax, &Assembler::uhsax, cond, rd, rn, rm);  in uhsax()
13154 void Assembler::uhsub16(Condition cond, Register rd, Register rn, Register rm) {  in uhsub16()  argument
13159     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub16()
13161                  rm.GetCode());  in uhsub16()
13168         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub16()
13170               (rn.GetCode() << 16) | rm.GetCode());  in uhsub16()
13174   Delegate(kUhsub16, &Assembler::uhsub16, cond, rd, rn, rm);  in uhsub16()
13177 void Assembler::uhsub8(Condition cond, Register rd, Register rn, Register rm) {  in uhsub8()  argument
13182     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub8()
13184                  rm.GetCode());  in uhsub8()
13191         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uhsub8()
13193               (rn.GetCode() << 16) | rm.GetCode());  in uhsub8()
13197   Delegate(kUhsub8, &Assembler::uhsub8, cond, rd, rn, rm);  in uhsub8()
13201     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umaal()  argument
13206     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umaal()
13209                  (rn.GetCode() << 16) | rm.GetCode());  in umaal()
13216         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umaal()
13220               (rm.GetCode() << 8));  in umaal()
13224   Delegate(kUmaal, &Assembler::umaal, cond, rdlo, rdhi, rn, rm);  in umaal()
13228     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umlal()  argument
13233     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umlal()
13236                  (rn.GetCode() << 16) | rm.GetCode());  in umlal()
13243         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umlal()
13247               (rm.GetCode() << 8));  in umlal()
13251   Delegate(kUmlal, &Assembler::umlal, cond, rdlo, rdhi, rn, rm);  in umlal()
13255     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umlals()  argument
13261         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umlals()
13265               (rm.GetCode() << 8));  in umlals()
13269   Delegate(kUmlals, &Assembler::umlals, cond, rdlo, rdhi, rn, rm);  in umlals()
13273     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umull()  argument
13278     if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umull()
13281                  (rn.GetCode() << 16) | rm.GetCode());  in umull()
13288         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umull()
13292               (rm.GetCode() << 8));  in umull()
13296   Delegate(kUmull, &Assembler::umull, cond, rdlo, rdhi, rn, rm);  in umull()
13300     Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {  in umulls()  argument
13306         ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||  in umulls()
13310               (rm.GetCode() << 8));  in umulls()
13314   Delegate(kUmulls, &Assembler::umulls, cond, rdlo, rdhi, rn, rm);  in umulls()
13317 void Assembler::uqadd16(Condition cond, Register rd, Register rn, Register rm) {  in uqadd16()  argument
13322     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd16()
13324                  rm.GetCode());  in uqadd16()
13331         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd16()
13333               (rn.GetCode() << 16) | rm.GetCode());  in uqadd16()
13337   Delegate(kUqadd16, &Assembler::uqadd16, cond, rd, rn, rm);  in uqadd16()
13340 void Assembler::uqadd8(Condition cond, Register rd, Register rn, Register rm) {  in uqadd8()  argument
13345     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd8()
13347                  rm.GetCode());  in uqadd8()
13354         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqadd8()
13356               (rn.GetCode() << 16) | rm.GetCode());  in uqadd8()
13360   Delegate(kUqadd8, &Assembler::uqadd8, cond, rd, rn, rm);  in uqadd8()
13363 void Assembler::uqasx(Condition cond, Register rd, Register rn, Register rm) {  in uqasx()  argument
13368     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqasx()
13370                  rm.GetCode());  in uqasx()
13377         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqasx()
13379               (rn.GetCode() << 16) | rm.GetCode());  in uqasx()
13383   Delegate(kUqasx, &Assembler::uqasx, cond, rd, rn, rm);  in uqasx()
13386 void Assembler::uqsax(Condition cond, Register rd, Register rn, Register rm) {  in uqsax()  argument
13391     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsax()
13393                  rm.GetCode());  in uqsax()
13400         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsax()
13402               (rn.GetCode() << 16) | rm.GetCode());  in uqsax()
13406   Delegate(kUqsax, &Assembler::uqsax, cond, rd, rn, rm);  in uqsax()
13409 void Assembler::uqsub16(Condition cond, Register rd, Register rn, Register rm) {  in uqsub16()  argument
13414     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub16()
13416                  rm.GetCode());  in uqsub16()
13423         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub16()
13425               (rn.GetCode() << 16) | rm.GetCode());  in uqsub16()
13429   Delegate(kUqsub16, &Assembler::uqsub16, cond, rd, rn, rm);  in uqsub16()
13432 void Assembler::uqsub8(Condition cond, Register rd, Register rn, Register rm) {  in uqsub8()  argument
13437     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub8()
13439                  rm.GetCode());  in uqsub8()
13446         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uqsub8()
13448               (rn.GetCode() << 16) | rm.GetCode());  in uqsub8()
13452   Delegate(kUqsub8, &Assembler::uqsub8, cond, rd, rn, rm);  in uqsub8()
13455 void Assembler::usad8(Condition cond, Register rd, Register rn, Register rm) {  in usad8()  argument
13460     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usad8()
13462                  rm.GetCode());  in usad8()
13469         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usad8()
13471               rn.GetCode() | (rm.GetCode() << 8));  in usad8()
13475   Delegate(kUsad8, &Assembler::usad8, cond, rd, rn, rm);  in usad8()
13479     Condition cond, Register rd, Register rn, Register rm, Register ra) {  in usada8()  argument
13485         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usada8()
13487                  rm.GetCode() | (ra.GetCode() << 12));  in usada8()
13494         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usada8()
13496               rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));  in usada8()
13500   Delegate(kUsada8, &Assembler::usada8, cond, rd, rn, rm, ra);  in usada8()
13579 void Assembler::usax(Condition cond, Register rd, Register rn, Register rm) {  in usax()  argument
13584     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usax()
13586                  rm.GetCode());  in usax()
13593         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usax()
13595               (rn.GetCode() << 16) | rm.GetCode());  in usax()
13599   Delegate(kUsax, &Assembler::usax, cond, rd, rn, rm);  in usax()
13602 void Assembler::usub16(Condition cond, Register rd, Register rn, Register rm) {  in usub16()  argument
13607     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub16()
13609                  rm.GetCode());  in usub16()
13616         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub16()
13618               (rn.GetCode() << 16) | rm.GetCode());  in usub16()
13622   Delegate(kUsub16, &Assembler::usub16, cond, rd, rn, rm);  in usub16()
13625 void Assembler::usub8(Condition cond, Register rd, Register rn, Register rm) {  in usub8()  argument
13630     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub8()
13632                  rm.GetCode());  in usub8()
13639         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in usub8()
13641               (rn.GetCode() << 16) | rm.GetCode());  in usub8()
13645   Delegate(kUsub8, &Assembler::usub8, cond, rd, rn, rm);  in usub8()
13655     Register rm = operand.GetBaseRegister();  in uxtab()  local
13662           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab()
13665                    rm.GetCode() | (amount_ << 4));  in uxtab()
13673           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab()
13676                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in uxtab()
13692     Register rm = operand.GetBaseRegister();  in uxtab16()  local
13699           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab16()
13702                    rm.GetCode() | (amount_ << 4));  in uxtab16()
13710           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtab16()
13713                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in uxtab16()
13729     Register rm = operand.GetBaseRegister();  in uxtah()  local
13736           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtah()
13739                    rm.GetCode() | (amount_ << 4));  in uxtah()
13747           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtah()
13750                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |  in uxtah()
13766     Register rm = operand.GetBaseRegister();  in uxtb()  local
13770         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in uxtb()
13771           EmitT32_16(0xb2c0 | rd.GetCode() | (rm.GetCode() << 3));  in uxtb()
13783           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb()
13785         EmitT32_32(0xfa5ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in uxtb()
13794           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb()
13797                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in uxtb()
13809     Register rm = operand.GetBaseRegister();  in uxtb16()  local
13816           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb16()
13818         EmitT32_32(0xfa3ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in uxtb16()
13827           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxtb16()
13830                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in uxtb16()
13845     Register rm = operand.GetBaseRegister();  in uxth()  local
13849         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {  in uxth()
13850           EmitT32_16(0xb280 | rd.GetCode() | (rm.GetCode() << 3));  in uxth()
13862           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxth()
13864         EmitT32_32(0xfa1ff080U | (rd.GetCode() << 8) | rm.GetCode() |  in uxth()
13873           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {  in uxth()
13876                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));  in uxth()
13885     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vaba()  argument
13895                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13906                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13911   Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);  in vaba()
13915     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vaba()  argument
13925                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13936                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaba()
13941   Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);  in vaba()
13945     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vabal()  argument
13955                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabal()
13966                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabal()
13971   Delegate(kVabal, &Assembler::vabal, cond, dt, rd, rn, rm);  in vabal()
13975     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vabd()  argument
13984                    rm.Encode(5, 0));  in vabd()
13994                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14004                 rm.Encode(5, 0));  in vabd()
14013                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14018   Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);  in vabd()
14022     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vabd()  argument
14031                    rm.Encode(5, 0));  in vabd()
14041                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14051                 rm.Encode(5, 0));  in vabd()
14060                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabd()
14065   Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);  in vabd()
14069     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vabdl()  argument
14079                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabdl()
14090                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vabdl()
14095   Delegate(kVabdl, &Assembler::vabdl, cond, dt, rd, rn, rm);  in vabdl()
14098 void Assembler::vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vabs()  argument
14108                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14115       EmitT32_32(0xeeb00bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14125                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14132               rm.Encode(5, 0));  in vabs()
14136   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);  in vabs()
14139 void Assembler::vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vabs()  argument
14149                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14160                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14165   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);  in vabs()
14168 void Assembler::vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) {  in vabs()  argument
14174       EmitT32_32(0xeeb00ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vabs()
14182               rm.Encode(5, 0));  in vabs()
14186   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);  in vabs()
14190     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vacge()  argument
14198                    rm.Encode(5, 0));  in vacge()
14208                 rm.Encode(5, 0));  in vacge()
14213   Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);  in vacge()
14217     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vacge()  argument
14225                    rm.Encode(5, 0));  in vacge()
14235                 rm.Encode(5, 0));  in vacge()
14240   Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);  in vacge()
14244     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vacgt()  argument
14252                    rm.Encode(5, 0));  in vacgt()
14262                 rm.Encode(5, 0));  in vacgt()
14267   Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);  in vacgt()
14271     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vacgt()  argument
14279                    rm.Encode(5, 0));  in vacgt()
14289                 rm.Encode(5, 0));  in vacgt()
14294   Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);  in vacgt()
14298     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vacle()  argument
14306                    rm.Encode(5, 0));  in vacle()
14316                 rm.Encode(5, 0));  in vacle()
14321   Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);  in vacle()
14325     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vacle()  argument
14333                    rm.Encode(5, 0));  in vacle()
14343                 rm.Encode(5, 0));  in vacle()
14348   Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);  in vacle()
14352     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vaclt()  argument
14360                    rm.Encode(5, 0));  in vaclt()
14370                 rm.Encode(5, 0));  in vaclt()
14375   Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);  in vaclt()
14379     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vaclt()  argument
14387                    rm.Encode(5, 0));  in vaclt()
14397                 rm.Encode(5, 0));  in vaclt()
14402   Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);  in vaclt()
14406     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vadd()  argument
14415                    rm.Encode(5, 0));  in vadd()
14423                  rm.Encode(5, 0));  in vadd()
14431                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14441                 rm.Encode(5, 0));  in vadd()
14448               rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14455                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14460   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);  in vadd()
14464     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vadd()  argument
14473                    rm.Encode(5, 0));  in vadd()
14482                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14492                 rm.Encode(5, 0));  in vadd()
14500                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14505   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);  in vadd()
14509     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vadd()  argument
14516                  rm.Encode(5, 0));  in vadd()
14524               rn.Encode(7, 16) | rm.Encode(5, 0));  in vadd()
14528   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);  in vadd()
14532     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vaddhn()  argument
14541                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddhn()
14551                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddhn()
14556   Delegate(kVaddhn, &Assembler::vaddhn, cond, dt, rd, rn, rm);  in vaddhn()
14560     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vaddl()  argument
14570                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddl()
14581                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddl()
14586   Delegate(kVaddl, &Assembler::vaddl, cond, dt, rd, rn, rm);  in vaddl()
14590     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {  in vaddw()  argument
14600                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddw()
14611                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vaddw()
14616   Delegate(kVaddw, &Assembler::vaddw, cond, dt, rd, rn, rm);  in vaddw()
14655     DRegister rm = operand.GetRegister();  in vand()  local
14661                    rm.Encode(5, 0));  in vand()
14669                 rm.Encode(5, 0));  in vand()
14713     QRegister rm = operand.GetRegister();  in vand()  local
14719                    rm.Encode(5, 0));  in vand()
14727                 rm.Encode(5, 0));  in vand()
14771     DRegister rm = operand.GetRegister();  in vbic()  local
14777                    rm.Encode(5, 0));  in vbic()
14785                 rm.Encode(5, 0));  in vbic()
14829     QRegister rm = operand.GetRegister();  in vbic()  local
14835                    rm.Encode(5, 0));  in vbic()
14843                 rm.Encode(5, 0));  in vbic()
14852     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vbif()  argument
14860                  rm.Encode(5, 0));  in vbif()
14868               rm.Encode(5, 0));  in vbif()
14872   Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);  in vbif()
14876     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vbif()  argument
14884                  rm.Encode(5, 0));  in vbif()
14892               rm.Encode(5, 0));  in vbif()
14896   Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);  in vbif()
14900     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vbit()  argument
14908                  rm.Encode(5, 0));  in vbit()
14916               rm.Encode(5, 0));  in vbit()
14920   Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);  in vbit()
14924     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vbit()  argument
14932                  rm.Encode(5, 0));  in vbit()
14940               rm.Encode(5, 0));  in vbit()
14944   Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);  in vbit()
14948     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vbsl()  argument
14956                  rm.Encode(5, 0));  in vbsl()
14964               rm.Encode(5, 0));  in vbsl()
14968   Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);  in vbsl()
14972     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vbsl()  argument
14980                  rm.Encode(5, 0));  in vbsl()
14988               rm.Encode(5, 0));  in vbsl()
14992   Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);  in vbsl()
14998                      DRegister rm,  in vceq()  argument
15013                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15025                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15032   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);  in vceq()
15038                      QRegister rm,  in vceq()  argument
15053                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15065                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vceq()
15072   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);  in vceq()
15076     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vceq()  argument
15086                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15095                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15105                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15113                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15118   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);  in vceq()
15122     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vceq()  argument
15132                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15141                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15151                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15159                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vceq()
15164   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);  in vceq()
15170                      DRegister rm,  in vcge()  argument
15185                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15197                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15204   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);  in vcge()
15210                      QRegister rm,  in vcge()  argument
15225                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15237                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcge()
15244   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);  in vcge()
15248     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vcge()  argument
15258                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15267                    rm.Encode(5, 0));  in vcge()
15278                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15286                 rm.Encode(5, 0));  in vcge()
15291   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);  in vcge()
15295     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vcge()  argument
15305                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15314                    rm.Encode(5, 0));  in vcge()
15325                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcge()
15333                 rm.Encode(5, 0));  in vcge()
15338   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);  in vcge()
15344                      DRegister rm,  in vcgt()  argument
15359                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15371                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15378   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);  in vcgt()
15384                      QRegister rm,  in vcgt()  argument
15399                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15411                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcgt()
15418   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);  in vcgt()
15422     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vcgt()  argument
15432                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15441                    rm.Encode(5, 0));  in vcgt()
15452                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15460                 rm.Encode(5, 0));  in vcgt()
15465   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);  in vcgt()
15469     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vcgt()  argument
15479                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15488                    rm.Encode(5, 0));  in vcgt()
15499                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vcgt()
15507                 rm.Encode(5, 0));  in vcgt()
15512   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);  in vcgt()
15518                      DRegister rm,  in vcle()  argument
15533                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15545                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15552   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);  in vcle()
15558                      QRegister rm,  in vcle()  argument
15573                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15585                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vcle()
15592   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);  in vcle()
15596     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vcle()  argument
15606                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15615                    rm.Encode(7, 16));  in vcle()
15626                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15634                 rm.Encode(7, 16));  in vcle()
15639   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);  in vcle()
15643     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vcle()  argument
15653                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15662                    rm.Encode(7, 16));  in vcle()
15673                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vcle()
15681                 rm.Encode(7, 16));  in vcle()
15686   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);  in vcle()
15689 void Assembler::vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vcls()  argument
15698                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15708                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15713   Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);  in vcls()
15716 void Assembler::vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vcls()  argument
15725                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15735                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcls()
15740   Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);  in vcls()
15746                      DRegister rm,  in vclt()  argument
15761                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15773                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15780   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);  in vclt()
15786                      QRegister rm,  in vclt()  argument
15801                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15813                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vclt()
15820   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);  in vclt()
15824     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vclt()  argument
15834                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15843                    rm.Encode(7, 16));  in vclt()
15854                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15862                 rm.Encode(7, 16));  in vclt()
15867   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);  in vclt()
15871     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vclt()  argument
15881                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15890                    rm.Encode(7, 16));  in vclt()
15901                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));  in vclt()
15909                 rm.Encode(7, 16));  in vclt()
15914   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);  in vclt()
15917 void Assembler::vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vclz()  argument
15926                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
15936                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
15941   Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);  in vclz()
15944 void Assembler::vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vclz()  argument
15953                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
15963                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vclz()
15968   Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);  in vclz()
15978     SRegister rm = operand.GetRegister();  in vcmp()  local
15982         EmitT32_32(0xeeb40a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmp()
15990                 rm.Encode(5, 0));  in vcmp()
16021     DRegister rm = operand.GetRegister();  in vcmp()  local
16025         EmitT32_32(0xeeb40b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmp()
16033                 rm.Encode(5, 0));  in vcmp()
16064     SRegister rm = operand.GetRegister();  in vcmpe()  local
16068         EmitT32_32(0xeeb40ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmpe()
16076                 rm.Encode(5, 0));  in vcmpe()
16107     DRegister rm = operand.GetRegister();  in vcmpe()  local
16111         EmitT32_32(0xeeb40bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcmpe()
16119                 rm.Encode(5, 0));  in vcmpe()
16143 void Assembler::vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vcnt()  argument
16150         EmitT32_32(0xffb00500U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16159         EmitA32(0xf3b00500U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16164   Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);  in vcnt()
16167 void Assembler::vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vcnt()  argument
16174         EmitT32_32(0xffb00540U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16183         EmitA32(0xf3b00540U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcnt()
16188   Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);  in vcnt()
16192     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {  in vcvt()  argument
16199       EmitT32_32(0xeeb70ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16206                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16214               rm.Encode(5, 0));  in vcvt()
16221               rm.Encode(5, 0));  in vcvt()
16225   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16229     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvt()  argument
16235       EmitT32_32(0xeeb70bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16241       EmitT32_32(0xeebc0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16247       EmitT32_32(0xeebd0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16255               rm.Encode(5, 0));  in vcvt()
16261               rm.Encode(5, 0));  in vcvt()
16267               rm.Encode(5, 0));  in vcvt()
16271   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16278                      DRegister rm,  in vcvt()  argument
16292                    rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16298     if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&  in vcvt()
16314     if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&  in vcvt()
16336                 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16341     if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&  in vcvt()
16358     if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&  in vcvt()
16375   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);  in vcvt()
16382                      QRegister rm,  in vcvt()  argument
16394                    rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16406                 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));  in vcvt()
16411   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);  in vcvt()
16418                      SRegister rm,  in vcvt()  argument
16426     if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&  in vcvt()
16442     if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&  in vcvt()
16459     if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&  in vcvt()
16476     if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&  in vcvt()
16493   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);  in vcvt()
16497     Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvt()  argument
16506                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16516                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16521   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16525     Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvt()  argument
16534                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16544                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16549   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16553     Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) {  in vcvt()  argument
16560         EmitT32_32(0xffb60600U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16569         EmitA32(0xf3b60600U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16574   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16578     Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) {  in vcvt()  argument
16585         EmitT32_32(0xffb60700U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16594         EmitA32(0xf3b60700U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16599   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16603     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvt()  argument
16610       EmitT32_32(0xeebc0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16616       EmitT32_32(0xeebd0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16623                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvt()
16631               rm.Encode(5, 0));  in vcvt()
16637               rm.Encode(5, 0));  in vcvt()
16644               rm.Encode(5, 0));  in vcvt()
16648   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);  in vcvt()
16651 void Assembler::vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvta()  argument
16659                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16667               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16671   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16674 void Assembler::vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvta()  argument
16682                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16690               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16694   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16697 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvta()  argument
16705                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16713               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16717   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16720 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvta()  argument
16728                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16736               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvta()
16740   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);  in vcvta()
16744     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtb()  argument
16750       EmitT32_32(0xeeb20a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16756       EmitT32_32(0xeeb30a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16764               rm.Encode(5, 0));  in vcvtb()
16770               rm.Encode(5, 0));  in vcvtb()
16774   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);  in vcvtb()
16778     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {  in vcvtb()  argument
16784       EmitT32_32(0xeeb20b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16792               rm.Encode(5, 0));  in vcvtb()
16796   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);  in vcvtb()
16800     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtb()  argument
16806       EmitT32_32(0xeeb30b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtb()
16814               rm.Encode(5, 0));  in vcvtb()
16818   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);  in vcvtb()
16821 void Assembler::vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvtm()  argument
16829                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16837               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16841   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16844 void Assembler::vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvtm()  argument
16852                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16860               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16864   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16867 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtm()  argument
16875                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16883               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16887   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16890 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtm()  argument
16898                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16906               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtm()
16910   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);  in vcvtm()
16913 void Assembler::vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvtn()  argument
16921                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16929               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16933   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
16936 void Assembler::vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvtn()  argument
16944                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16952               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16956   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
16959 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtn()  argument
16967                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16975               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16979   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
16982 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtn()  argument
16990                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
16998               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtn()
17002   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);  in vcvtn()
17005 void Assembler::vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {  in vcvtp()  argument
17013                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17021               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17025   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17028 void Assembler::vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {  in vcvtp()  argument
17036                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17044               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17048   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17051 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtp()  argument
17059                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17067               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17071   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17074 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtp()  argument
17082                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17090               rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtp()
17094   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);  in vcvtp()
17098     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtr()  argument
17104       EmitT32_32(0xeebc0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17110       EmitT32_32(0xeebd0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17118               rm.Encode(5, 0));  in vcvtr()
17124               rm.Encode(5, 0));  in vcvtr()
17128   Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);  in vcvtr()
17132     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtr()  argument
17138       EmitT32_32(0xeebc0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17144       EmitT32_32(0xeebd0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtr()
17152               rm.Encode(5, 0));  in vcvtr()
17158               rm.Encode(5, 0));  in vcvtr()
17162   Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);  in vcvtr()
17166     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {  in vcvtt()  argument
17172       EmitT32_32(0xeeb20ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17178       EmitT32_32(0xeeb30ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17186               rm.Encode(5, 0));  in vcvtt()
17192               rm.Encode(5, 0));  in vcvtt()
17196   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);  in vcvtt()
17200     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {  in vcvtt()  argument
17206       EmitT32_32(0xeeb20bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17214               rm.Encode(5, 0));  in vcvtt()
17218   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);  in vcvtt()
17222     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {  in vcvtt()  argument
17228       EmitT32_32(0xeeb30bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vcvtt()
17236               rm.Encode(5, 0));  in vcvtt()
17240   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);  in vcvtt()
17244     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vdiv()  argument
17251                  rm.Encode(5, 0));  in vdiv()
17259               rn.Encode(7, 16) | rm.Encode(5, 0));  in vdiv()
17263   Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);  in vdiv()
17267     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vdiv()  argument
17274                  rm.Encode(5, 0));  in vdiv()
17282               rn.Encode(7, 16) | rm.Encode(5, 0));  in vdiv()
17286   Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);  in vdiv()
17354                      DRegisterLane rm) {  in vdup()  argument
17357   Dt_imm4_1 encoded_dt(dt, rm);  in vdup()
17363                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17373                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17378   Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);  in vdup()
17384                      DRegisterLane rm) {  in vdup()  argument
17387   Dt_imm4_1 encoded_dt(dt, rm);  in vdup()
17393                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17403                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vdup()
17408   Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);  in vdup()
17412     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in veor()  argument
17420                  rm.Encode(5, 0));  in veor()
17428               rm.Encode(5, 0));  in veor()
17432   Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);  in veor()
17436     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in veor()  argument
17444                  rm.Encode(5, 0));  in veor()
17452               rm.Encode(5, 0));  in veor()
17456   Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);  in veor()
17463                      DRegister rm,  in vext()  argument
17475                        rm.Encode(5, 0) | (imm << 8));  in vext()
17486                        rm.Encode(5, 0) | (imm4 << 8));  in vext()
17496                     rm.Encode(5, 0) | (imm << 8));  in vext()
17506                     rm.Encode(5, 0) | (imm4 << 8));  in vext()
17513   Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);  in vext()
17520                      QRegister rm,  in vext()  argument
17532                        rm.Encode(5, 0) | (imm << 8));  in vext()
17543                        rm.Encode(5, 0) | (imm4 << 8));  in vext()
17553                     rm.Encode(5, 0) | (imm << 8));  in vext()
17563                     rm.Encode(5, 0) | (imm4 << 8));  in vext()
17570   Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);  in vext()
17574     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfma()  argument
17582                    rm.Encode(5, 0));  in vfma()
17590                  rm.Encode(5, 0));  in vfma()
17599                 rm.Encode(5, 0));  in vfma()
17606               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfma()
17610   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);  in vfma()
17614     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vfma()  argument
17622                    rm.Encode(5, 0));  in vfma()
17632                 rm.Encode(5, 0));  in vfma()
17637   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);  in vfma()
17641     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfma()  argument
17648                  rm.Encode(5, 0));  in vfma()
17656               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfma()
17660   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);  in vfma()
17664     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfms()  argument
17672                    rm.Encode(5, 0));  in vfms()
17680                  rm.Encode(5, 0));  in vfms()
17689                 rm.Encode(5, 0));  in vfms()
17696               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfms()
17700   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);  in vfms()
17704     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vfms()  argument
17712                    rm.Encode(5, 0));  in vfms()
17722                 rm.Encode(5, 0));  in vfms()
17727   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);  in vfms()
17731     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfms()  argument
17738                  rm.Encode(5, 0));  in vfms()
17746               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfms()
17750   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);  in vfms()
17754     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfnma()  argument
17761                  rm.Encode(5, 0));  in vfnma()
17769               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnma()
17773   Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);  in vfnma()
17777     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfnma()  argument
17784                  rm.Encode(5, 0));  in vfnma()
17792               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnma()
17796   Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);  in vfnma()
17800     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vfnms()  argument
17807                  rm.Encode(5, 0));  in vfnms()
17815               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnms()
17819   Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);  in vfnms()
17823     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vfnms()  argument
17830                  rm.Encode(5, 0));  in vfnms()
17838               rn.Encode(7, 16) | rm.Encode(5, 0));  in vfnms()
17842   Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);  in vfnms()
17846     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vhadd()  argument
17856                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17867                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17872   Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);  in vhadd()
17876     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vhadd()  argument
17886                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17897                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhadd()
17902   Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);  in vhadd()
17906     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vhsub()  argument
17916                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17927                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17932   Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);  in vhsub()
17936     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vhsub()  argument
17946                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17957                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vhsub()
17962   Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);  in vhsub()
18224     Register rm = operand.GetOffsetRegister();  in vld1()  local
18234           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18257                      (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18265           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18272                      (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18279           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vld1()
18286                      rm.GetCode());  in vld1()
18295           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18318                   (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18325           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld1()
18332                   (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18338           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vld1()
18344                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld1()
18603     Register rm = operand.GetOffsetRegister();  in vld2()  local
18614           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18630                      (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18639           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18646                      (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18655           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18661                      rm.GetCode());  in vld2()
18672           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18688                   (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18696           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18703                   (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18711           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld2()
18716                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld2()
18809     Register rm = operand.GetOffsetRegister();  in vld3()  local
18817           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld3()
18824                      (rn.GetCode() << 16) | rm.GetCode());  in vld3()
18834           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld3()
18841                   (rn.GetCode() << 16) | rm.GetCode());  in vld3()
18979     Register rm = operand.GetOffsetRegister();  in vld3()  local
18994                      (rn.GetCode() << 16) | rm.GetCode());  in vld3()
19010                      rm.GetCode());  in vld3()
19027                   (rn.GetCode() << 16) | rm.GetCode());  in vld3()
19041                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld3()
19261     Register rm = operand.GetOffsetRegister();  in vld4()  local
19272           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19279                      (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19288           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19295                      (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19304           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19310                      rm.GetCode());  in vld4()
19320           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19327                   (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19335           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19342                   (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19350           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vld4()
19355                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vld4()
19880     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmax()  argument
19889                    rm.Encode(5, 0));  in vmax()
19899                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
19909                 rm.Encode(5, 0));  in vmax()
19918                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
19923   Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);  in vmax()
19927     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmax()  argument
19936                    rm.Encode(5, 0));  in vmax()
19946                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
19956                 rm.Encode(5, 0));  in vmax()
19965                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmax()
19970   Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);  in vmax()
19973 void Assembler::vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmaxnm()  argument
19980                  rm.Encode(5, 0));  in vmaxnm()
19987                  rm.Encode(5, 0));  in vmaxnm()
19995               rm.Encode(5, 0));  in vmaxnm()
20001               rm.Encode(5, 0));  in vmaxnm()
20005   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);  in vmaxnm()
20008 void Assembler::vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmaxnm()  argument
20015                  rm.Encode(5, 0));  in vmaxnm()
20023               rm.Encode(5, 0));  in vmaxnm()
20027   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);  in vmaxnm()
20030 void Assembler::vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmaxnm()  argument
20037                  rm.Encode(5, 0));  in vmaxnm()
20045               rm.Encode(5, 0));  in vmaxnm()
20049   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);  in vmaxnm()
20053     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmin()  argument
20062                    rm.Encode(5, 0));  in vmin()
20072                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20082                 rm.Encode(5, 0));  in vmin()
20091                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20096   Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);  in vmin()
20100     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmin()  argument
20109                    rm.Encode(5, 0));  in vmin()
20119                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20129                 rm.Encode(5, 0));  in vmin()
20138                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmin()
20143   Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);  in vmin()
20146 void Assembler::vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vminnm()  argument
20153                  rm.Encode(5, 0));  in vminnm()
20160                  rm.Encode(5, 0));  in vminnm()
20168               rm.Encode(5, 0));  in vminnm()
20174               rm.Encode(5, 0));  in vminnm()
20178   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);  in vminnm()
20181 void Assembler::vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vminnm()  argument
20188                  rm.Encode(5, 0));  in vminnm()
20196               rm.Encode(5, 0));  in vminnm()
20200   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);  in vminnm()
20203 void Assembler::vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vminnm()  argument
20210                  rm.Encode(5, 0));  in vminnm()
20218               rm.Encode(5, 0));  in vminnm()
20222   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);  in vminnm()
20226     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vmla()  argument
20233         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20234          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20235           (rm.GetLane() <= 1)))) {  in vmla()
20239                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20247         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20248          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20249           (rm.GetLane() <= 1)))) {  in vmla()
20253                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20258   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20262     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vmla()  argument
20269         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20270          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20271           (rm.GetLane() <= 1)))) {  in vmla()
20275                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20283         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmla()
20284          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmla()
20285           (rm.GetLane() <= 1)))) {  in vmla()
20289                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmla()
20294   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20298     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmla()  argument
20307                    rm.Encode(5, 0));  in vmla()
20315                  rm.Encode(5, 0));  in vmla()
20323                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20333                 rm.Encode(5, 0));  in vmla()
20340               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20347                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20352   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20356     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmla()  argument
20365                    rm.Encode(5, 0));  in vmla()
20374                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20384                 rm.Encode(5, 0));  in vmla()
20392                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20397   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20401     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmla()  argument
20408                  rm.Encode(5, 0));  in vmla()
20416               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmla()
20420   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);  in vmla()
20424     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {  in vmlal()  argument
20431         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlal()
20432          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlal()
20433           (rm.GetLane() <= 1)))) {  in vmlal()
20437                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlal()
20445         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlal()
20446          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlal()
20447           (rm.GetLane() <= 1)))) {  in vmlal()
20451                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlal()
20456   Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);  in vmlal()
20460     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vmlal()  argument
20470                    rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlal()
20481                 rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlal()
20486   Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);  in vmlal()
20490     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vmls()  argument
20497         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20498          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20499           (rm.GetLane() <= 1)))) {  in vmls()
20503                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20511         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20512          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20513           (rm.GetLane() <= 1)))) {  in vmls()
20517                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20522   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20526     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vmls()  argument
20533         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20534          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20535           (rm.GetLane() <= 1)))) {  in vmls()
20539                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20547         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmls()
20548          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmls()
20549           (rm.GetLane() <= 1)))) {  in vmls()
20553                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmls()
20558   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20562     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmls()  argument
20571                    rm.Encode(5, 0));  in vmls()
20579                  rm.Encode(5, 0));  in vmls()
20587                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20597                 rm.Encode(5, 0));  in vmls()
20604               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20611                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20616   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20620     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmls()  argument
20629                    rm.Encode(5, 0));  in vmls()
20638                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20648                 rm.Encode(5, 0));  in vmls()
20656                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20661   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20665     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmls()  argument
20672                  rm.Encode(5, 0));  in vmls()
20680               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmls()
20684   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);  in vmls()
20688     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {  in vmlsl()  argument
20695         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlsl()
20696          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlsl()
20697           (rm.GetLane() <= 1)))) {  in vmlsl()
20701                    rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlsl()
20709         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vmlsl()
20710          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vmlsl()
20711           (rm.GetLane() <= 1)))) {  in vmlsl()
20715                 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vmlsl()
20720   Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);  in vmlsl()
20724     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vmlsl()  argument
20734                    rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlsl()
20745                 rn.Encode(7, 16) | rm.Encode(5, 0));  in vmlsl()
20750   Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);  in vmlsl()
20795 void Assembler::vmov(Condition cond, Register rt, Register rt2, DRegister rm) {  in vmov()  argument
20802                  rm.Encode(5, 0));  in vmov()
20811               (rt2.GetCode() << 16) | rm.Encode(5, 0));  in vmov()
20815   Delegate(kVmov, &Assembler::vmov, cond, rt, rt2, rm);  in vmov()
20818 void Assembler::vmov(Condition cond, DRegister rm, Register rt, Register rt2) {  in vmov()  argument
20824       EmitT32_32(0xec400b10U | rm.Encode(5, 0) | (rt.GetCode() << 12) |  in vmov()
20833       EmitA32(0x0c400b10U | (cond.GetCondition() << 28) | rm.Encode(5, 0) |  in vmov()
20838   Delegate(kVmov, &Assembler::vmov, cond, rm, rt, rt2);  in vmov()
20842     Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1) {  in vmov()  argument
20847     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20850                  rm.Encode(5, 0));  in vmov()
20856     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20860               (rt2.GetCode() << 16) | rm.Encode(5, 0));  in vmov()
20864   Delegate(kVmov, &Assembler::vmov, cond, rt, rt2, rm, rm1);  in vmov()
20868     Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2) {  in vmov()  argument
20873     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20875       EmitT32_32(0xec400a10U | rm.Encode(5, 0) | (rt.GetCode() << 12) |  in vmov()
20882     if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&  in vmov()
20885       EmitA32(0x0c400a10U | (cond.GetCondition() << 28) | rm.Encode(5, 0) |  in vmov()
20890   Delegate(kVmov, &Assembler::vmov, cond, rm, rm1, rt, rt2);  in vmov()
20981     DRegister rm = operand.GetRegister();  in vmov()  local
20985         EmitT32_32(0xeeb00b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmov()
20992           EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
20993                      rm.Encode(5, 0));  in vmov()
21002                 rm.Encode(5, 0));  in vmov()
21008           EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
21009                   rm.Encode(5, 0));  in vmov()
21055     QRegister rm = operand.GetRegister();  in vmov()  local
21060           EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
21061                      rm.Encode(5, 0));  in vmov()
21070           EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vmov()
21071                   rm.Encode(5, 0));  in vmov()
21108     SRegister rm = operand.GetRegister();  in vmov()  local
21112         EmitT32_32(0xeeb00a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmov()
21120                 rm.Encode(5, 0));  in vmov()
21160 void Assembler::vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) {  in vmovl()  argument
21170                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovl()
21181                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovl()
21186   Delegate(kVmovl, &Assembler::vmovl, cond, dt, rd, rm);  in vmovl()
21189 void Assembler::vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {  in vmovn()  argument
21198                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovn()
21208                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vmovn()
21213   Delegate(kVmovn, &Assembler::vmovn, cond, dt, rd, rm);  in vmovn()
21360     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vmul()  argument
21369                    rm.Encode(5, 0));  in vmul()
21377                  rm.Encode(5, 0));  in vmul()
21386                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21396                 rm.Encode(5, 0));  in vmul()
21403               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21411                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21416   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);  in vmul()
21420     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vmul()  argument
21429                    rm.Encode(5, 0));  in vmul()
21439                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21449                 rm.Encode(5, 0));  in vmul()
21458                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21463   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);  in vmul()
21467     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vmul()  argument
21474                  rm.Encode(5, 0));  in vmul()
21482               rn.Encode(7, 16) | rm.Encode(5, 0));  in vmul()
21486   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);  in vmul()
21542     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vmull()  argument
21553                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmull()
21565                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vmull()
21570   Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, rm);  in vmull()
21608     DRegister rm = operand.GetRegister();  in vmvn()  local
21613         EmitT32_32(0xffb00580U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21620         EmitA32(0xf3b00580U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21663     QRegister rm = operand.GetRegister();  in vmvn()  local
21668         EmitT32_32(0xffb005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21675         EmitA32(0xf3b005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vmvn()
21683 void Assembler::vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vneg()  argument
21693                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21700       EmitT32_32(0xeeb10b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21710                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21717               rm.Encode(5, 0));  in vneg()
21721   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);  in vneg()
21724 void Assembler::vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vneg()  argument
21734                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21745                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21750   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);  in vneg()
21753 void Assembler::vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) {  in vneg()  argument
21759       EmitT32_32(0xeeb10a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vneg()
21767               rm.Encode(5, 0));  in vneg()
21771   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);  in vneg()
21775     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vnmla()  argument
21782                  rm.Encode(5, 0));  in vnmla()
21790               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmla()
21794   Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);  in vnmla()
21798     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vnmla()  argument
21805                  rm.Encode(5, 0));  in vnmla()
21813               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmla()
21817   Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);  in vnmla()
21821     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vnmls()  argument
21828                  rm.Encode(5, 0));  in vnmls()
21836               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmls()
21840   Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);  in vnmls()
21844     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vnmls()  argument
21851                  rm.Encode(5, 0));  in vnmls()
21859               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmls()
21863   Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);  in vnmls()
21867     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vnmul()  argument
21874                  rm.Encode(5, 0));  in vnmul()
21882               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmul()
21886   Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);  in vnmul()
21890     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vnmul()  argument
21897                  rm.Encode(5, 0));  in vnmul()
21905               rn.Encode(7, 16) | rm.Encode(5, 0));  in vnmul()
21909   Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);  in vnmul()
21948     DRegister rm = operand.GetRegister();  in vorn()  local
21954                    rm.Encode(5, 0));  in vorn()
21962                 rm.Encode(5, 0));  in vorn()
22006     QRegister rm = operand.GetRegister();  in vorn()  local
22012                    rm.Encode(5, 0));  in vorn()
22020                 rm.Encode(5, 0));  in vorn()
22036     DRegister rm = operand.GetRegister();  in vorr()  local
22042                    rm.Encode(5, 0));  in vorr()
22050                 rm.Encode(5, 0));  in vorr()
22094     QRegister rm = operand.GetRegister();  in vorr()  local
22100                    rm.Encode(5, 0));  in vorr()
22108                 rm.Encode(5, 0));  in vorr()
22147                        DRegister rm) {  in vpadal()  argument
22157                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22168                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22173   Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);  in vpadal()
22179                        QRegister rm) {  in vpadal()  argument
22189                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22200                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpadal()
22205   Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);  in vpadal()
22209     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vpadd()  argument
22218                    rm.Encode(5, 0));  in vpadd()
22227                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpadd()
22237                 rm.Encode(5, 0));  in vpadd()
22245                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpadd()
22250   Delegate(kVpadd, &Assembler::vpadd, cond, dt, rd, rn, rm);  in vpadd()
22256                        DRegister rm) {  in vpaddl()  argument
22266                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22277                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22282   Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);  in vpaddl()
22288                        QRegister rm) {  in vpaddl()  argument
22298                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22309                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vpaddl()
22314   Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);  in vpaddl()
22318     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vpmax()  argument
22327                    rm.Encode(5, 0));  in vpmax()
22337                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmax()
22347                 rm.Encode(5, 0));  in vpmax()
22356                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmax()
22361   Delegate(kVpmax, &Assembler::vpmax, cond, dt, rd, rn, rm);  in vpmax()
22365     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vpmin()  argument
22374                    rm.Encode(5, 0));  in vpmin()
22384                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmin()
22394                 rm.Encode(5, 0));  in vpmin()
22403                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vpmin()
22408   Delegate(kVpmin, &Assembler::vpmin, cond, dt, rd, rn, rm);  in vpmin()
22513 void Assembler::vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vqabs()  argument
22522                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22532                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22537   Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);  in vqabs()
22540 void Assembler::vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vqabs()  argument
22549                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22559                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqabs()
22564   Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);  in vqabs()
22568     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqadd()  argument
22578                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22589                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22594   Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);  in vqadd()
22598     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqadd()  argument
22608                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22619                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqadd()
22624   Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);  in vqadd()
22628     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vqdmlal()  argument
22637                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlal()
22647                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlal()
22652   Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, rm);  in vqdmlal()
22706     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vqdmlsl()  argument
22715                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlsl()
22725                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmlsl()
22730   Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, rm);  in vqdmlsl()
22784     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqdmulh()  argument
22793                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22803                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22808   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22812     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqdmulh()  argument
22821                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22831                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmulh()
22836   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22840     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vqdmulh()  argument
22847         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22848          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22849           (rm.GetLane() <= 1))) &&  in vqdmulh()
22853                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22861         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22862          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22863           (rm.GetLane() <= 1))) &&  in vqdmulh()
22867                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22872   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22876     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vqdmulh()  argument
22883         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22884          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22885           (rm.GetLane() <= 1))) &&  in vqdmulh()
22889                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22897         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmulh()
22898          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmulh()
22899           (rm.GetLane() <= 1))) &&  in vqdmulh()
22903                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmulh()
22908   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);  in vqdmulh()
22912     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vqdmull()  argument
22921                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmull()
22931                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqdmull()
22936   Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);  in vqdmull()
22940     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {  in vqdmull()  argument
22947         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmull()
22948          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmull()
22949           (rm.GetLane() <= 1))) &&  in vqdmull()
22953                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmull()
22961         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqdmull()
22962          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqdmull()
22963           (rm.GetLane() <= 1))) &&  in vqdmull()
22967                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqdmull()
22972   Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);  in vqdmull()
22978                        QRegister rm) {  in vqmovn()  argument
22988                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovn()
22999                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovn()
23004   Delegate(kVqmovn, &Assembler::vqmovn, cond, dt, rd, rm);  in vqmovn()
23010                         QRegister rm) {  in vqmovun()  argument
23019                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovun()
23029                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqmovun()
23034   Delegate(kVqmovun, &Assembler::vqmovun, cond, dt, rd, rm);  in vqmovun()
23037 void Assembler::vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vqneg()  argument
23046                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23056                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23061   Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);  in vqneg()
23064 void Assembler::vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vqneg()  argument
23073                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23083                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vqneg()
23088   Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);  in vqneg()
23092     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqrdmulh()  argument
23101                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23111                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23116   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23120     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqrdmulh()  argument
23129                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23139                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqrdmulh()
23144   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23148     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {  in vqrdmulh()  argument
23155         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23156          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23157           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23161                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23169         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23170          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23171           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23175                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23180   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23184     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {  in vqrdmulh()  argument
23191         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23192          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23193           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23197                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23205         (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||  in vqrdmulh()
23206          ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&  in vqrdmulh()
23207           (rm.GetLane() <= 1))) &&  in vqrdmulh()
23211                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));  in vqrdmulh()
23216   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);  in vqrdmulh()
23220     Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {  in vqrshl()  argument
23230                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23241                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23246   Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);  in vqrshl()
23250     Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {  in vqrshl()  argument
23260                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23271                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqrshl()
23276   Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);  in vqrshl()
23282                         QRegister rm,  in vqrshrn()  argument
23298                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrn()
23310                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrn()
23322                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrn()
23332                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrn()
23339   Delegate(kVqrshrn, &Assembler::vqrshrn, cond, dt, rd, rm, operand);  in vqrshrn()
23345                          QRegister rm,  in vqrshrun()  argument
23361                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrun()
23370                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrun()
23382                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqrshrun()
23390                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqrshrun()
23397   Delegate(kVqrshrun, &Assembler::vqrshrun, cond, dt, rd, rm, operand);  in vqrshrun()
23403                       DRegister rm,  in vqshl()  argument
23417                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23428                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23446                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23459                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23466   Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);  in vqshl()
23472                       QRegister rm,  in vqshl()  argument
23486                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23497                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vqshl()
23515                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23528                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshl()
23535   Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);  in vqshl()
23541                        DRegister rm,  in vqshlu()  argument
23557                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23570                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23577   Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);  in vqshlu()
23583                        QRegister rm,  in vqshlu()  argument
23599                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23612                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshlu()
23619   Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);  in vqshlu()
23625                        QRegister rm,  in vqshrn()  argument
23641                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrn()
23653                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrn()
23665                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrn()
23675                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrn()
23682   Delegate(kVqshrn, &Assembler::vqshrn, cond, dt, rd, rm, operand);  in vqshrn()
23688                         QRegister rm,  in vqshrun()  argument
23704                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrun()
23713                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrun()
23725                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vqshrun()
23733                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vqshrun()
23740   Delegate(kVqshrun, &Assembler::vqshrun, cond, dt, rd, rm, operand);  in vqshrun()
23744     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vqsub()  argument
23754                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23765                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23770   Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);  in vqsub()
23774     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vqsub()  argument
23784                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23795                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vqsub()
23800   Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);  in vqsub()
23804     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vraddhn()  argument
23813                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vraddhn()
23823                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vraddhn()
23828   Delegate(kVraddhn, &Assembler::vraddhn, cond, dt, rd, rn, rm);  in vraddhn()
23834                        DRegister rm) {  in vrecpe()  argument
23844                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23855                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23860   Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);  in vrecpe()
23866                        QRegister rm) {  in vrecpe()  argument
23876                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23887                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrecpe()
23892   Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);  in vrecpe()
23896     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vrecps()  argument
23904                    rm.Encode(5, 0));  in vrecps()
23914                 rm.Encode(5, 0));  in vrecps()
23919   Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);  in vrecps()
23923     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vrecps()  argument
23931                    rm.Encode(5, 0));  in vrecps()
23941                 rm.Encode(5, 0));  in vrecps()
23946   Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);  in vrecps()
23952                        DRegister rm) {  in vrev16()  argument
23961                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
23971                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
23976   Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);  in vrev16()
23982                        QRegister rm) {  in vrev16()  argument
23991                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
24001                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev16()
24006   Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);  in vrev16()
24012                        DRegister rm) {  in vrev32()  argument
24021                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24031                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24036   Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);  in vrev32()
24042                        QRegister rm) {  in vrev32()  argument
24051                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24061                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev32()
24066   Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);  in vrev32()
24072                        DRegister rm) {  in vrev64()  argument
24081                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24091                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24096   Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);  in vrev64()
24102                        QRegister rm) {  in vrev64()  argument
24111                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24121                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrev64()
24126   Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);  in vrev64()
24130     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vrhadd()  argument
24140                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24151                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24156   Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);  in vrhadd()
24160     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vrhadd()  argument
24170                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24181                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrhadd()
24186   Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);  in vrhadd()
24189 void Assembler::vrinta(DataType dt, DRegister rd, DRegister rm) {  in vrinta()  argument
24197                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24203       EmitT32_32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24211               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24216       EmitA32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24220   Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);  in vrinta()
24223 void Assembler::vrinta(DataType dt, QRegister rd, QRegister rm) {  in vrinta()  argument
24231                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24239               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24243   Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);  in vrinta()
24246 void Assembler::vrinta(DataType dt, SRegister rd, SRegister rm) {  in vrinta()  argument
24252       EmitT32_32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24259       EmitA32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrinta()
24263   Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);  in vrinta()
24266 void Assembler::vrintm(DataType dt, DRegister rd, DRegister rm) {  in vrintm()  argument
24274                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24280       EmitT32_32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24288               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24293       EmitA32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24297   Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);  in vrintm()
24300 void Assembler::vrintm(DataType dt, QRegister rd, QRegister rm) {  in vrintm()  argument
24308                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24316               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24320   Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);  in vrintm()
24323 void Assembler::vrintm(DataType dt, SRegister rd, SRegister rm) {  in vrintm()  argument
24329       EmitT32_32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24336       EmitA32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintm()
24340   Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);  in vrintm()
24343 void Assembler::vrintn(DataType dt, DRegister rd, DRegister rm) {  in vrintn()  argument
24351                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24357       EmitT32_32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24365               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24370       EmitA32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24374   Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);  in vrintn()
24377 void Assembler::vrintn(DataType dt, QRegister rd, QRegister rm) {  in vrintn()  argument
24385                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24393               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24397   Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);  in vrintn()
24400 void Assembler::vrintn(DataType dt, SRegister rd, SRegister rm) {  in vrintn()  argument
24406       EmitT32_32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24413       EmitA32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintn()
24417   Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);  in vrintn()
24420 void Assembler::vrintp(DataType dt, DRegister rd, DRegister rm) {  in vrintp()  argument
24428                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24434       EmitT32_32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24442               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24447       EmitA32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24451   Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);  in vrintp()
24454 void Assembler::vrintp(DataType dt, QRegister rd, QRegister rm) {  in vrintp()  argument
24462                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24470               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24474   Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);  in vrintp()
24477 void Assembler::vrintp(DataType dt, SRegister rd, SRegister rm) {  in vrintp()  argument
24483       EmitT32_32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24490       EmitA32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintp()
24494   Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);  in vrintp()
24500                        SRegister rm) {  in vrintr()  argument
24506       EmitT32_32(0xeeb60a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintr()
24514               rm.Encode(5, 0));  in vrintr()
24518   Delegate(kVrintr, &Assembler::vrintr, cond, dt, rd, rm);  in vrintr()
24524                        DRegister rm) {  in vrintr()  argument
24530       EmitT32_32(0xeeb60b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintr()
24538               rm.Encode(5, 0));  in vrintr()
24542   Delegate(kVrintr, &Assembler::vrintr, cond, dt, rd, rm);  in vrintr()
24548                        DRegister rm) {  in vrintx()  argument
24556                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24562       EmitT32_32(0xeeb70b40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24570               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24576               rm.Encode(5, 0));  in vrintx()
24580   Delegate(kVrintx, &Assembler::vrintx, cond, dt, rd, rm);  in vrintx()
24583 void Assembler::vrintx(DataType dt, QRegister rd, QRegister rm) {  in vrintx()  argument
24591                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24599               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24603   Delegate(kVrintx, &Assembler::vrintx, dt, rd, rm);  in vrintx()
24609                        SRegister rm) {  in vrintx()  argument
24615       EmitT32_32(0xeeb70a40U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintx()
24623               rm.Encode(5, 0));  in vrintx()
24627   Delegate(kVrintx, &Assembler::vrintx, cond, dt, rd, rm);  in vrintx()
24633                        DRegister rm) {  in vrintz()  argument
24641                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24647       EmitT32_32(0xeeb60bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24655               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24661               rm.Encode(5, 0));  in vrintz()
24665   Delegate(kVrintz, &Assembler::vrintz, cond, dt, rd, rm);  in vrintz()
24668 void Assembler::vrintz(DataType dt, QRegister rd, QRegister rm) {  in vrintz()  argument
24676                  rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24684               rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24688   Delegate(kVrintz, &Assembler::vrintz, dt, rd, rm);  in vrintz()
24694                        SRegister rm) {  in vrintz()  argument
24700       EmitT32_32(0xeeb60ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vrintz()
24708               rm.Encode(5, 0));  in vrintz()
24712   Delegate(kVrintz, &Assembler::vrintz, cond, dt, rd, rm);  in vrintz()
24716     Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {  in vrshl()  argument
24726                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24737                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24742   Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);  in vrshl()
24746     Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {  in vrshl()  argument
24756                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24767                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vrshl()
24772   Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);  in vrshl()
24778                       DRegister rm,  in vrshr()  argument
24794                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24802             EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24803                        rm.Encode(5, 0));  in vrshr()
24816                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24823             EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24824                     rm.Encode(5, 0));  in vrshr()
24831   Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);  in vrshr()
24837                       QRegister rm,  in vrshr()  argument
24853                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24861             EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24862                        rm.Encode(5, 0));  in vrshr()
24875                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshr()
24882             EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vrshr()
24883                     rm.Encode(5, 0));  in vrshr()
24890   Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);  in vrshr()
24896                        QRegister rm,  in vrshrn()  argument
24912                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshrn()
24921                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vrshrn()
24933                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrshrn()
24941                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vrshrn()
24948   Delegate(kVrshrn, &Assembler::vrshrn, cond, dt, rd, rm, operand);  in vrshrn()
24954                         DRegister rm) {  in vrsqrte()  argument
24964                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
24975                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
24980   Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);  in vrsqrte()
24986                         QRegister rm) {  in vrsqrte()  argument
24996                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
25007                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vrsqrte()
25012   Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);  in vrsqrte()
25016     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vrsqrts()  argument
25024                    rm.Encode(5, 0));  in vrsqrts()
25034                 rm.Encode(5, 0));  in vrsqrts()
25039   Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);  in vrsqrts()
25043     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vrsqrts()  argument
25051                    rm.Encode(5, 0));  in vrsqrts()
25061                 rm.Encode(5, 0));  in vrsqrts()
25066   Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);  in vrsqrts()
25072                       DRegister rm,  in vrsra()  argument
25088                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25101                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25108   Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);  in vrsra()
25114                       QRegister rm,  in vrsra()  argument
25130                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25143                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vrsra()
25150   Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);  in vrsra()
25154     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vrsubhn()  argument
25163                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrsubhn()
25173                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vrsubhn()
25178   Delegate(kVrsubhn, &Assembler::vrsubhn, cond, dt, rd, rn, rm);  in vrsubhn()
25181 void Assembler::vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vseleq()  argument
25188                  rm.Encode(5, 0));  in vseleq()
25196               rm.Encode(5, 0));  in vseleq()
25200   Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);  in vseleq()
25203 void Assembler::vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vseleq()  argument
25210                  rm.Encode(5, 0));  in vseleq()
25218               rm.Encode(5, 0));  in vseleq()
25222   Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);  in vseleq()
25225 void Assembler::vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vselge()  argument
25232                  rm.Encode(5, 0));  in vselge()
25240               rm.Encode(5, 0));  in vselge()
25244   Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);  in vselge()
25247 void Assembler::vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vselge()  argument
25254                  rm.Encode(5, 0));  in vselge()
25262               rm.Encode(5, 0));  in vselge()
25266   Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);  in vselge()
25269 void Assembler::vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vselgt()  argument
25276                  rm.Encode(5, 0));  in vselgt()
25284               rm.Encode(5, 0));  in vselgt()
25288   Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);  in vselgt()
25291 void Assembler::vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vselgt()  argument
25298                  rm.Encode(5, 0));  in vselgt()
25306               rm.Encode(5, 0));  in vselgt()
25310   Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);  in vselgt()
25313 void Assembler::vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vselvs()  argument
25320                  rm.Encode(5, 0));  in vselvs()
25328               rm.Encode(5, 0));  in vselvs()
25332   Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);  in vselvs()
25335 void Assembler::vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vselvs()  argument
25342                  rm.Encode(5, 0));  in vselvs()
25350               rm.Encode(5, 0));  in vselvs()
25354   Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);  in vselvs()
25360                      DRegister rm,  in vshl()  argument
25376                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25389                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25406                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25417                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25423   Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);  in vshl()
25429                      QRegister rm,  in vshl()  argument
25445                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25458                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshl()
25475                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25486                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));  in vshl()
25492   Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);  in vshl()
25498                       DRegister rm,  in vshll()  argument
25514                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshll()
25523                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vshll()
25535                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshll()
25543                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vshll()
25550   Delegate(kVshll, &Assembler::vshll, cond, dt, rd, rm, operand);  in vshll()
25556                      DRegister rm,  in vshr()  argument
25572                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25580             EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25581                        rm.Encode(5, 0));  in vshr()
25594                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25601             EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25602                     rm.Encode(5, 0));  in vshr()
25609   Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);  in vshr()
25615                      QRegister rm,  in vshr()  argument
25631                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25639             EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25640                        rm.Encode(5, 0));  in vshr()
25653                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshr()
25660             EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |  in vshr()
25661                     rm.Encode(5, 0));  in vshr()
25668   Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);  in vshr()
25674                       QRegister rm,  in vshrn()  argument
25690                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshrn()
25699                        rd.Encode(22, 12) | rm.Encode(5, 0));  in vshrn()
25711                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vshrn()
25719                     rd.Encode(22, 12) | rm.Encode(5, 0));  in vshrn()
25726   Delegate(kVshrn, &Assembler::vshrn, cond, dt, rd, rm, operand);  in vshrn()
25732                      DRegister rm,  in vsli()  argument
25748                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25761                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25768   Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);  in vsli()
25774                      QRegister rm,  in vsli()  argument
25790                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25803                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsli()
25810   Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);  in vsli()
25813 void Assembler::vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) {  in vsqrt()  argument
25819       EmitT32_32(0xeeb10ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vsqrt()
25827               rm.Encode(5, 0));  in vsqrt()
25831   Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);  in vsqrt()
25834 void Assembler::vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vsqrt()  argument
25840       EmitT32_32(0xeeb10bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vsqrt()
25848               rm.Encode(5, 0));  in vsqrt()
25852   Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);  in vsqrt()
25858                      DRegister rm,  in vsra()  argument
25874                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25887                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25894   Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);  in vsra()
25900                      QRegister rm,  in vsra()  argument
25916                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25929                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsra()
25936   Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);  in vsra()
25942                      DRegister rm,  in vsri()  argument
25958                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
25971                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
25978   Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);  in vsri()
25984                      QRegister rm,  in vsri()  argument
26000                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
26013                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));  in vsri()
26020   Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);  in vsri()
26219     Register rm = operand.GetOffsetRegister();  in vst1()  local
26228           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst1()
26251                      (rn.GetCode() << 16) | rm.GetCode());  in vst1()
26258           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vst1()
26265                      rm.GetCode());  in vst1()
26274           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst1()
26297                   (rn.GetCode() << 16) | rm.GetCode());  in vst1()
26303           (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&  in vst1()
26309                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst1()
26501     Register rm = operand.GetOffsetRegister();  in vst2()  local
26511           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26527                      (rn.GetCode() << 16) | rm.GetCode());  in vst2()
26536           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26542                      rm.GetCode());  in vst2()
26553           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26569                   (rn.GetCode() << 16) | rm.GetCode());  in vst2()
26577           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst2()
26582                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst2()
26675     Register rm = operand.GetOffsetRegister();  in vst3()  local
26683           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst3()
26690                      (rn.GetCode() << 16) | rm.GetCode());  in vst3()
26700           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst3()
26707                   (rn.GetCode() << 16) | rm.GetCode());  in vst3()
26787     Register rm = operand.GetOffsetRegister();  in vst3()  local
26802                      rm.GetCode());  in vst3()
26818                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst3()
26970     Register rm = operand.GetOffsetRegister();  in vst4()  local
26979           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
26986                      (rn.GetCode() << 16) | rm.GetCode());  in vst4()
26995           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
27001                      rm.GetCode());  in vst4()
27011           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
27018                   (rn.GetCode() << 16) | rm.GetCode());  in vst4()
27026           !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {  in vst4()
27031                   first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());  in vst4()
27320     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vsub()  argument
27329                    rm.Encode(5, 0));  in vsub()
27337                  rm.Encode(5, 0));  in vsub()
27345                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27355                 rm.Encode(5, 0));  in vsub()
27362               rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27369                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27374   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);  in vsub()
27378     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vsub()  argument
27387                    rm.Encode(5, 0));  in vsub()
27396                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27406                 rm.Encode(5, 0));  in vsub()
27414                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27419   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);  in vsub()
27423     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {  in vsub()  argument
27430                  rm.Encode(5, 0));  in vsub()
27438               rn.Encode(7, 16) | rm.Encode(5, 0));  in vsub()
27442   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);  in vsub()
27446     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {  in vsubhn()  argument
27455                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubhn()
27465                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubhn()
27470   Delegate(kVsubhn, &Assembler::vsubhn, cond, dt, rd, rn, rm);  in vsubhn()
27474     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {  in vsubl()  argument
27484                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubl()
27495                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubl()
27500   Delegate(kVsubl, &Assembler::vsubl, cond, dt, rd, rn, rm);  in vsubl()
27504     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {  in vsubw()  argument
27514                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubw()
27525                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vsubw()
27530   Delegate(kVsubw, &Assembler::vsubw, cond, dt, rd, rn, rm);  in vsubw()
27533 void Assembler::vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vswp()  argument
27540       EmitT32_32(0xffb20000U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27547       EmitA32(0xf3b20000U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27551   Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);  in vswp()
27554 void Assembler::vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vswp()  argument
27561       EmitT32_32(0xffb20040U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27568       EmitA32(0xf3b20040U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vswp()
27572   Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);  in vswp()
27579                      DRegister rm) {  in vtbl()  argument
27590                    (len_encoding << 8) | rm.Encode(5, 0));  in vtbl()
27603                 (len_encoding << 8) | rm.Encode(5, 0));  in vtbl()
27608   Delegate(kVtbl, &Assembler::vtbl, cond, dt, rd, nreglist, rm);  in vtbl()
27615                      DRegister rm) {  in vtbx()  argument
27626                    (len_encoding << 8) | rm.Encode(5, 0));  in vtbx()
27639                 (len_encoding << 8) | rm.Encode(5, 0));  in vtbx()
27644   Delegate(kVtbx, &Assembler::vtbx, cond, dt, rd, nreglist, rm);  in vtbx()
27647 void Assembler::vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vtrn()  argument
27656                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27666                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27671   Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);  in vtrn()
27674 void Assembler::vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vtrn()  argument
27683                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27693                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vtrn()
27698   Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);  in vtrn()
27702     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {  in vtst()  argument
27711                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27721                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27726   Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);  in vtst()
27730     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {  in vtst()  argument
27739                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27749                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));  in vtst()
27754   Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);  in vtst()
27757 void Assembler::vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vuzp()  argument
27766                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27774         EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27784                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27791         EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27796   Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);  in vuzp()
27799 void Assembler::vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vuzp()  argument
27808                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27818                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vuzp()
27823   Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);  in vuzp()
27826 void Assembler::vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) {  in vzip()  argument
27835                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27843         EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27853                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27860         EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27865   Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);  in vzip()
27868 void Assembler::vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) {  in vzip()  argument
27877                    rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27887                 rd.Encode(22, 12) | rm.Encode(5, 0));  in vzip()
27892   Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);  in vzip()