Lines Matching refs:fpreg
196 const FPRegister& fpreg) { in EqualFP16() argument
197 VIXL_ASSERT(fpreg.Is16Bits()); in EqualFP16()
200 uint64_t result_64 = core->dreg_bits(fpreg.GetCode()); in EqualFP16()
208 return EqualFP16(expected, core, core->hreg(fpreg.GetCode())); in EqualFP16()
214 const FPRegister& fpreg) { in EqualFP32() argument
215 VIXL_ASSERT(fpreg.Is32Bits()); in EqualFP32()
218 uint64_t result_64 = core->dreg_bits(fpreg.GetCode()); in EqualFP32()
227 return EqualFP32(expected, core, core->sreg(fpreg.GetCode())); in EqualFP32()
233 const FPRegister& fpreg) { in EqualFP64() argument
234 VIXL_ASSERT(fpreg.Is64Bits()); in EqualFP64()
235 return EqualFP64(expected, core, core->dreg(fpreg.GetCode())); in EqualFP64()