Lines Matching refs:v2
272 define <4 x float> @_Z4fmaxDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readonly {
273 …%1 = tail call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %v1, <4 x float> %v2) nounwind r…
277 define <4 x float> @_Z4fmaxDv4_ff(<4 x float> %v1, float %v2) nounwind readonly {
278 %1 = tail call <4 x float> @smear_4f(float %v2) nounwind readnone
283 define <3 x float> @_Z4fmaxDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readonly {
285 %2 = shufflevector <3 x float> %v2, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
291 define <3 x float> @_Z4fmaxDv3_ff(<3 x float> %v1, float %v2) nounwind readonly {
293 %2 = tail call <4 x float> @smear_4f(float %v2) nounwind readnone
299 define <2 x float> @_Z4fmaxDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readonly {
300 …%1 = tail call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %v1, <2 x float> %v2) nounwind r…
304 define <2 x float> @_Z4fmaxDv2_ff(<2 x float> %v1, float %v2) nounwind readonly {
305 %1 = tail call <2 x float> @smear_2f(float %v2) nounwind readnone
310 define float @_Z4fmaxff(float %v1, float %v2) nounwind readonly {
311 %1 = fcmp ogt float %v1, %v2
312 %2 = select i1 %1, float %v1, float %v2
321 define <4 x float> @_Z4fminDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readonly {
322 …%1 = tail call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %v1, <4 x float> %v2) nounwind r…
326 define <4 x float> @_Z4fminDv4_ff(<4 x float> %v1, float %v2) nounwind readonly {
327 %1 = tail call <4 x float> @smear_4f(float %v2) nounwind readnone
332 define <3 x float> @_Z4fminDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readonly {
334 %2 = shufflevector <3 x float> %v2, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
340 define <3 x float> @_Z4fminDv3_ff(<3 x float> %v1, float %v2) nounwind readonly {
342 %2 = tail call <4 x float> @smear_4f(float %v2) nounwind readnone
348 define <2 x float> @_Z4fminDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readonly {
349 …%1 = tail call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %v1, <2 x float> %v2) nounwind r…
353 define <2 x float> @_Z4fminDv2_ff(<2 x float> %v1, float %v2) nounwind readonly {
354 %1 = tail call <2 x float> @smear_2f(float %v2) nounwind readnone
359 define float @_Z4fminff(float %v1, float %v2) nounwind readnone {
360 %1 = fcmp olt float %v1, %v2
361 %2 = select i1 %1, float %v1, float %v2
370 define signext i8 @_Z3maxcc(i8 signext %v1, i8 signext %v2) nounwind readnone {
371 %1 = icmp sgt i8 %v1, %v2
372 %2 = select i1 %1, i8 %v1, i8 %v2
376 define <2 x i8> @_Z3maxDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
378 %2 = sext <2 x i8> %v2 to <2 x i32>
384 define <3 x i8> @_Z3maxDv3_cS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
386 %2 = sext <3 x i8> %v2 to <3 x i32>
395 define <4 x i8> @_Z3maxDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
397 %2 = sext <4 x i8> %v2 to <4 x i32>
403 define signext i16 @_Z3maxss(i16 signext %v1, i16 signext %v2) nounwind readnone {
404 %1 = icmp sgt i16 %v1, %v2
405 %2 = select i1 %1, i16 %v1, i16 %v2
409 define <2 x i16> @_Z3maxDv2_sS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
411 %2 = sext <2 x i16> %v2 to <2 x i32>
417 define <3 x i16> @_Z3maxDv3_sS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
419 %2 = sext <3 x i16> %v2 to <3 x i32>
428 define <4 x i16> @_Z3maxDv4_sS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
430 %2 = sext <4 x i16> %v2 to <4 x i32>
436 define i32 @_Z3maxii(i32 %v1, i32 %v2) nounwind readnone {
437 %1 = icmp sgt i32 %v1, %v2
438 %2 = select i1 %1, i32 %v1, i32 %v2
442 define <2 x i32> @_Z3maxDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
443 …%1 = tail call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
447 define <3 x i32> @_Z3maxDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
449 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
455 define <4 x i32> @_Z3maxDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
456 …%1 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
460 define i64 @_Z3maxxx(i64 %v1, i64 %v2) nounwind readnone {
461 %1 = icmp sgt i64 %v1, %v2
462 %2 = select i1 %1, i64 %v1, i64 %v2
468 define zeroext i8 @_Z3maxhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
469 %1 = icmp ugt i8 %v1, %v2
470 %2 = select i1 %1, i8 %v1, i8 %v2
474 define <2 x i8> @_Z3maxDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
476 %2 = zext <2 x i8> %v2 to <2 x i32>
482 define <3 x i8> @_Z3maxDv3_hS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
484 %2 = zext <3 x i8> %v2 to <3 x i32>
493 define <4 x i8> @_Z3maxDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
495 %2 = zext <4 x i8> %v2 to <4 x i32>
501 define zeroext i16 @_Z3maxtt(i16 zeroext %v1, i16 zeroext %v2) nounwind readnone {
502 %1 = icmp ugt i16 %v1, %v2
503 %2 = select i1 %1, i16 %v1, i16 %v2
507 define <2 x i16> @_Z3maxDv2_tS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
509 %2 = zext <2 x i16> %v2 to <2 x i32>
515 define <3 x i16> @_Z3maxDv3_tS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
517 %2 = zext <3 x i16> %v2 to <3 x i32>
526 define <4 x i16> @_Z3maxDv4_tS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
528 %2 = zext <4 x i16> %v2 to <4 x i32>
534 define i32 @_Z3maxjj(i32 %v1, i32 %v2) nounwind readnone {
535 %1 = icmp ugt i32 %v1, %v2
536 %2 = select i1 %1, i32 %v1, i32 %v2
540 define <2 x i32> @_Z3maxDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
541 …%1 = tail call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
545 define <3 x i32> @_Z3maxDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
547 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
553 define <4 x i32> @_Z3maxDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
554 …%1 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
561 define float @_Z3maxff(float %v1, float %v2) nounwind readnone {
562 %1 = tail call float @_Z4fmaxff(float %v1, float %v2)
566 define <2 x float> @_Z3maxDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readnone {
567 %1 = tail call <2 x float> @_Z4fmaxDv2_fS_(<2 x float> %v1, <2 x float> %v2)
571 define <2 x float> @_Z3maxDv2_ff(<2 x float> %v1, float %v2) nounwind readnone {
572 %1 = tail call <2 x float> @_Z4fmaxDv2_ff(<2 x float> %v1, float %v2)
576 define <3 x float> @_Z3maxDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readnone {
577 %1 = tail call <3 x float> @_Z4fmaxDv3_fS_(<3 x float> %v1, <3 x float> %v2)
581 define <3 x float> @_Z3maxDv3_ff(<3 x float> %v1, float %v2) nounwind readnone {
582 %1 = tail call <3 x float> @_Z4fmaxDv3_ff(<3 x float> %v1, float %v2)
586 define <4 x float> @_Z3maxDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readnone {
587 %1 = tail call <4 x float> @_Z4fmaxDv4_fS_(<4 x float> %v1, <4 x float> %v2)
591 define <4 x float> @_Z3maxDv4_ff(<4 x float> %v1, float %v2) nounwind readnone {
592 %1 = tail call <4 x float> @_Z4fmaxDv4_ff(<4 x float> %v1, float %v2)
601 define signext i8 @_Z3mincc(i8 signext %v1, i8 signext %v2) nounwind readnone {
602 %1 = icmp slt i8 %v1, %v2
603 %2 = select i1 %1, i8 %v1, i8 %v2
607 define <2 x i8> @_Z3minDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
609 %2 = sext <2 x i8> %v2 to <2 x i32>
615 define <3 x i8> @_Z3minDv3_cS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
617 %2 = sext <3 x i8> %v2 to <3 x i32>
626 define <4 x i8> @_Z3minDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
628 %2 = sext <4 x i8> %v2 to <4 x i32>
634 define signext i16 @_Z3minss(i16 signext %v1, i16 signext %v2) nounwind readnone {
635 %1 = icmp slt i16 %v1, %v2
636 %2 = select i1 %1, i16 %v1, i16 %v2
640 define <2 x i16> @_Z3minDv2_sS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
642 %2 = sext <2 x i16> %v2 to <2 x i32>
648 define <3 x i16> @_Z3minDv3_sS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
650 %2 = sext <3 x i16> %v2 to <3 x i32>
659 define <4 x i16> @_Z3minDv4_sS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
661 %2 = sext <4 x i16> %v2 to <4 x i32>
667 define i32 @_Z3minii(i32 %v1, i32 %v2) nounwind readnone {
668 %1 = icmp slt i32 %v1, %v2
669 %2 = select i1 %1, i32 %v1, i32 %v2
673 define <2 x i32> @_Z3minDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
674 …%1 = tail call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
678 define <3 x i32> @_Z3minDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
680 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
686 define <4 x i32> @_Z3minDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
687 …%1 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
691 define i64 @_Z3minxx(i64 %v1, i64 %v2) nounwind readnone {
692 %1 = icmp slt i64 %v1, %v2
693 %2 = select i1 %1, i64 %v1, i64 %v2
699 define zeroext i8 @_Z3minhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
700 %1 = icmp ult i8 %v1, %v2
701 %2 = select i1 %1, i8 %v1, i8 %v2
705 define <2 x i8> @_Z3minDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
707 %2 = zext <2 x i8> %v2 to <2 x i32>
713 define <3 x i8> @_Z3minDv3_hS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
715 %2 = zext <3 x i8> %v2 to <3 x i32>
724 define <4 x i8> @_Z3minDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
726 %2 = zext <4 x i8> %v2 to <4 x i32>
732 define zeroext i16 @_Z3mintt(i16 zeroext %v1, i16 zeroext %v2) nounwind readnone {
733 %1 = icmp ult i16 %v1, %v2
734 %2 = select i1 %1, i16 %v1, i16 %v2
738 define <2 x i16> @_Z3minDv2_tS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
740 %2 = zext <2 x i16> %v2 to <2 x i32>
746 define <3 x i16> @_Z3minDv3_tS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
748 %2 = zext <3 x i16> %v2 to <3 x i32>
757 define <4 x i16> @_Z3minDv4_tS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
759 %2 = zext <4 x i16> %v2 to <4 x i32>
765 define i32 @_Z3minjj(i32 %v1, i32 %v2) nounwind readnone {
766 %1 = icmp ult i32 %v1, %v2
767 %2 = select i1 %1, i32 %v1, i32 %v2
771 define <2 x i32> @_Z3minDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
772 …%1 = tail call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
776 define <3 x i32> @_Z3minDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
778 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
784 define <4 x i32> @_Z3minDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
785 …%1 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
792 define float @_Z3minff(float %v1, float %v2) nounwind readnone {
793 %1 = tail call float @_Z4fminff(float %v1, float %v2)
797 define <2 x float> @_Z3minDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readnone {
798 %1 = tail call <2 x float> @_Z4fminDv2_fS_(<2 x float> %v1, <2 x float> %v2)
802 define <2 x float> @_Z3minDv2_ff(<2 x float> %v1, float %v2) nounwind readnone {
803 %1 = tail call <2 x float> @_Z4fminDv2_ff(<2 x float> %v1, float %v2)
807 define <3 x float> @_Z3minDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readnone {
808 %1 = tail call <3 x float> @_Z4fminDv3_fS_(<3 x float> %v1, <3 x float> %v2)
812 define <3 x float> @_Z3minDv3_ff(<3 x float> %v1, float %v2) nounwind readnone {
813 %1 = tail call <3 x float> @_Z4fminDv3_ff(<3 x float> %v1, float %v2)
817 define <4 x float> @_Z3minDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readnone {
818 %1 = tail call <4 x float> @_Z4fminDv4_fS_(<4 x float> %v1, <4 x float> %v2)
822 define <4 x float> @_Z3minDv4_ff(<4 x float> %v1, float %v2) nounwind readnone {
823 %1 = tail call <4 x float> @_Z4fminDv4_ff(<4 x float> %v1, float %v2)
1104 %v2 = fadd <4 x float> %f05, %v1
1105 …%v3 = tail call <4 x float> @_Z5clampDv4_fS_S_(<4 x float> %v2, <4 x float> %f0, <4 x float> %f255…