Lines Matching refs:shift
373 uint32_t shift; in dataProcessingCommon() local
379 shift = mAddrMode.reg_imm_type; in dataProcessingCommon()
385 shift = 0; in dataProcessingCommon()
397 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
398 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
399 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
400 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
401 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break; in dataProcessingCommon()
884 uint32_t ArmToArm64Assembler::reg_imm(int Rm, int type, uint32_t shift) in reg_imm() argument
888 mAddrMode.reg_imm_shift = shift; in reg_imm()
925 uint32_t shift, int W) in reg_scale_pre() argument
927 if(type != 0 || shift != 0 || W != 0) in reg_scale_pre()
1073 uint32_t Rm, uint32_t shift, in A64_ADD_X() argument
1077 Rd, Rn, Rm, shift_codes[shift], amount); in A64_ADD_X()
1078 return ((0x8B << 24) | (shift << 22) | ( Rm << 16) | in A64_ADD_X()
1082 uint32_t imm, uint32_t shift) in A64_ADD_IMM_X() argument
1084 LOG_INSTR("ADD X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift); in A64_ADD_IMM_X()
1085 return (0x91 << 24) | ((shift/12) << 22) | (imm << 10) | (Rn << 5) | Rd; in A64_ADD_IMM_X()
1089 uint32_t imm, uint32_t shift) in A64_SUB_IMM_X() argument
1091 LOG_INSTR("SUB X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift); in A64_SUB_IMM_X()
1092 return (0xD1 << 24) | ((shift/12) << 22) | (imm << 10) | (Rn << 5) | Rd; in A64_SUB_IMM_X()
1096 uint32_t Rm, uint32_t shift, in A64_ADD_W() argument
1100 Rd, Rn, Rm, shift_codes[shift], amount); in A64_ADD_W()
1101 return ((0x0B << 24) | (shift << 22) | ( Rm << 16) | in A64_ADD_W()
1106 uint32_t Rm, uint32_t shift, in A64_SUB_W() argument
1113 Rd, Rn, Rm, shift_codes[shift], amount); in A64_SUB_W()
1114 return ((0x4B << 24) | (shift << 22) | ( Rm << 16) | in A64_SUB_W()
1120 Rd, Rn, Rm, shift_codes[shift], amount); in A64_SUB_W()
1121 return ((0x6B << 24) | (shift << 22) | ( Rm << 16) | in A64_SUB_W()
1127 uint32_t Rm, uint32_t shift, in A64_AND_W() argument
1131 Rd, Rn, Rm, shift_codes[shift], amount); in A64_AND_W()
1132 return ((0x0A << 24) | (shift << 22) | ( Rm << 16) | in A64_AND_W()
1137 uint32_t Rm, uint32_t shift, in A64_ORR_W() argument
1141 Rd, Rn, Rm, shift_codes[shift], amount); in A64_ORR_W()
1142 return ((0x2A << 24) | (shift << 22) | ( Rm << 16) | in A64_ORR_W()
1147 uint32_t Rm, uint32_t shift, in A64_ORN_W() argument
1151 Rd, Rn, Rm, shift_codes[shift], amount); in A64_ORN_W()
1152 return ((0x2A << 24) | (shift << 22) | (0x1 << 21) | ( Rm << 16) | in A64_ORN_W()
1177 uint32_t shift) in A64_MOVZ_X() argument
1179 LOG_INSTR("MOVZ X%d, #0x%x, LSL #%d\n", Rd, imm, shift); in A64_MOVZ_X()
1180 return(0xD2 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd; in A64_MOVZ_X()
1184 uint32_t shift) in A64_MOVK_W() argument
1186 LOG_INSTR("MOVK W%d, #0x%x, LSL #%d\n", Rd, imm, shift); in A64_MOVK_W()
1187 return (0x72 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd; in A64_MOVK_W()
1191 uint32_t shift) in A64_MOVZ_W() argument
1193 LOG_INSTR("MOVZ W%d, #0x%x, LSL #%d\n", Rd, imm, shift); in A64_MOVZ_W()
1194 return(0x52 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd; in A64_MOVZ_W()