Lines Matching refs:Rd
334 void ArmToMips64Assembler::protectConditionalOperands(int Rd) in protectConditionalOperands() argument
336 if (Rd == cond.r1) { in protectConditionalOperands()
340 if (cond.type == CMP_COND && Rd == cond.r2) { in protectConditionalOperands()
392 int s, int Rd, int Rn, uint32_t Op2) in dataProcessing() argument
397 protectConditionalOperands(Rd); in dataProcessing()
408 mMips->AND(Rd, Rn, src); in dataProcessing()
410 mMips->ANDI(Rd, Rn, src); in dataProcessing()
417 mMips->ADDU(Rd, Rn, src); in dataProcessing()
419 mMips->ADDIU(Rd, Rn, src); in dataProcessing()
426 mMips->SUBU(Rd, Rn, src); in dataProcessing()
428 mMips->SUBIU(Rd, Rn, src); in dataProcessing()
435 mMips->DADDU(Rd, Rn, src); in dataProcessing()
437 mMips->DADDIU(Rd, Rn, src); in dataProcessing()
444 mMips->DSUBU(Rd, Rn, src); in dataProcessing()
446 mMips->DSUBIU(Rd, Rn, src); in dataProcessing()
452 mMips->XOR(Rd, Rn, src); in dataProcessing()
454 mMips->XORI(Rd, Rn, src); in dataProcessing()
460 mMips->OR(Rd, Rn, src); in dataProcessing()
462 mMips->ORI(Rd, Rn, src); in dataProcessing()
473 mMips->AND(Rd, Rn, R_at); in dataProcessing()
482 mMips->SUBU(Rd, src, Rn); // subu with the parameters reversed in dataProcessing()
487 mMips->MOVE(Rd, Op2); in dataProcessing()
490 mMips->LUI(Rd, (amode.value >> 16)); in dataProcessing()
492 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff)); in dataProcessing()
495 mMips->ORI(Rd, 0, amode.value); in dataProcessing()
499 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
500 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; in dataProcessing()
501 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; in dataProcessing()
502 case ROR: mMips->ROTR(Rd, amode.reg, amode.value); break; in dataProcessing()
513 mMips->NOR(Rd, Op2, 0); // NOT is NOR with 0 in dataProcessing()
517 mMips->LUI(Rd, (amode.value >> 16)); in dataProcessing()
519 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff)); in dataProcessing()
522 mMips->ORI(Rd, 0, amode.value); in dataProcessing()
526 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
527 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; in dataProcessing()
528 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; in dataProcessing()
529 case ROR: mMips->ROTR(Rd, amode.reg, amode.value); break; in dataProcessing()
536 mMips->NOR(Rd, Rd, 0); // NOT is NOR with 0 in dataProcessing()
582 cond.r1 = Rd; in dataProcessing()
595 int Rd, int Rm, int Rs, int Rn) { in MLA() argument
601 mMips->ADDU(Rd, R_at, Rn); in MLA()
604 cond.r1 = Rd; in MLA()
609 int Rd, int Rm, int Rs) { in MUL() argument
611 mMips->MUL(Rd, Rm, Rs); in MUL()
614 cond.r1 = Rd; in MUL()
750 void ArmToMips64Assembler::LDR(int cc __unused, int Rd, int Rn, uint32_t offset) in LDR() argument
764 mMips->LW(Rd, Rn, amode.value); in LDR()
773 mMips->LW(Rd, Rn, 0); in LDR()
779 mMips->LW(Rd, R_at, 0); in LDR()
784 void ArmToMips64Assembler::LDRB(int cc __unused, int Rd, int Rn, uint32_t offset) in LDRB() argument
795 mMips->LBU(Rd, Rn, amode.value); in LDRB()
801 mMips->LBU(Rd, Rn, 0); in LDRB()
807 mMips->LBU(Rd, R_at, 0); in LDRB()
813 void ArmToMips64Assembler::STR(int cc __unused, int Rd, int Rn, uint32_t offset) in STR() argument
831 mMips->SW(Rd, Rn, 0); in STR()
834 mMips->SW(Rd, Rn, amode.value); in STR()
838 mMips->SW(Rd, Rn, 0); in STR()
844 mMips->SW(Rd, R_at, 0); in STR()
849 void ArmToMips64Assembler::STRB(int cc __unused, int Rd, int Rn, uint32_t offset) in STRB() argument
860 mMips->SB(Rd, Rn, amode.value); in STRB()
866 mMips->SB(Rd, Rn, 0); in STRB()
872 mMips->SB(Rd, R_at, 0); in STRB()
877 void ArmToMips64Assembler::LDRH(int cc __unused, int Rd, int Rn, uint32_t offset) in LDRH() argument
887 mMips->LHU(Rd, Rn, amode.value); in LDRH()
890 mMips->LHU(Rd, Rn, 0); in LDRH()
900 mMips->LHU(Rd, R_at, 0); in LDRH()
905 void ArmToMips64Assembler::LDRSB(int cc __unused, int Rd __unused, in LDRSB()
913 void ArmToMips64Assembler::LDRSH(int cc __unused, int Rd __unused, in LDRSH()
921 void ArmToMips64Assembler::STRH(int cc __unused, int Rd, int Rn, uint32_t offset) in STRH() argument
931 mMips->SH(Rd, Rn, amode.value); in STRH()
934 mMips->SH(Rd, Rn, 0); in STRH()
944 mMips->SH(Rd, R_at, 0); in STRH()
990 int Rd __unused, int Rm __unused) { in SWP()
998 int Rd __unused, int Rm __unused) { in SWPB()
1028 void ArmToMips64Assembler::CLZ(int cc __unused, int Rd, int Rm) in CLZ() argument
1031 mMips->CLZ(Rd, Rm); in CLZ()
1034 void ArmToMips64Assembler::QADD(int cc __unused, int Rd __unused, in QADD()
1043 void ArmToMips64Assembler::QDADD(int cc __unused, int Rd __unused, in QDADD()
1052 void ArmToMips64Assembler::QSUB(int cc __unused, int Rd __unused, in QSUB()
1061 void ArmToMips64Assembler::QDSUB(int cc __unused, int Rd __unused, in QDSUB()
1072 int Rd, int Rm, int Rs) in SMUL() argument
1096 mMips->MUL(Rd, R_at, R_at2); in SMUL()
1101 int Rd, int Rm, int Rs) in SMULW() argument
1115 mMips->MUH(Rd, Rm, R_at); in SMULW()
1120 int Rd, int Rm, int Rs, int Rn) in SMLA() argument
1146 mMips->ADDU(Rd, R_at, Rn); in SMLA()
1160 int Rd __unused, int Rm __unused, in SMLAW()
1170 void ArmToMips64Assembler::UXTB16(int cc __unused, int Rd, int Rm, int rotate) in UXTB16() argument
1180 mMips->AND(Rd, R_at2, R_at); in UXTB16()
1183 void ArmToMips64Assembler::UBFX(int cc __unused, int Rd __unused, int Rn __unused, in UBFX()
1198 int s, int Rd, int Rn, uint32_t Op2) in ADDR_ADD() argument
1202 dataProcessing(opADD64, cc, s, Rd, Rn, Op2); in ADDR_ADD()
1206 int s, int Rd, int Rn, uint32_t Op2) in ADDR_SUB() argument
1210 dataProcessing(opSUB64, cc, s, Rd, Rn, Op2); in ADDR_SUB()
1213 void ArmToMips64Assembler::ADDR_LDR(int cc __unused, int Rd, in ADDR_LDR() argument
1227 mMips->LD(Rd, Rn, amode.value); in ADDR_LDR()
1236 mMips->LD(Rd, Rn, 0); in ADDR_LDR()
1242 mMips->LD(Rd, R_at, 0); in ADDR_LDR()
1247 void ArmToMips64Assembler::ADDR_STR(int cc __unused, int Rd, in ADDR_STR() argument
1265 mMips->SD(Rd, Rn, 0); in ADDR_STR()
1268 mMips->SD(Rd, Rn, amode.value); in ADDR_STR()
1272 mMips->SD(Rd, Rn, 0); in ADDR_STR()
1278 mMips->SD(Rd, R_at, 0); in ADDR_STR()
1379 void MIPS64Assembler::DADDU(int Rd, int Rs, int Rt) in DADDU() argument
1382 | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF); in DADDU()
1390 void MIPS64Assembler::DSUBU(int Rd, int Rs, int Rt) in DSUBU() argument
1393 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in DSUBU()
1401 void MIPS64Assembler::MUL(int Rd, int Rs, int Rt) in MUL() argument
1404 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in MUL()
1407 void MIPS64Assembler::MUH(int Rd, int Rs, int Rt) in MUH() argument
1410 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in MUH()
1413 void MIPS64Assembler::CLO(int Rd, int Rs) in CLO() argument
1416 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (1<<RE_SHF); in CLO()
1419 void MIPS64Assembler::CLZ(int Rd, int Rs) in CLZ() argument
1422 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (1<<RE_SHF); in CLZ()