Lines Matching refs:amode
217 amode.value = immediate; in imm()
223 amode.reg = Rm; in reg_imm()
224 amode.stype = type; in reg_imm()
225 amode.value = shift; in reg_imm()
250 amode.value = immed12; in immed12_pre()
251 amode.writeback = W; in immed12_pre()
261 amode.value = immed12; in immed12_post()
270 amode.reg = Rm; in reg_scale_pre()
300 amode.value = immed8; in immed8_post()
307 amode.reg = Rm; in reg_pre()
362 if ((!_signed && amode.value > 0xffff) in dataProcAdrModes()
363 || (_signed && ((int)amode.value < -32768 || (int)amode.value > 32767) )) { in dataProcAdrModes()
364 mMips->LUI(tmpReg, (amode.value >> 16)); in dataProcAdrModes()
365 if (amode.value & 0x0000ffff) { in dataProcAdrModes()
366 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff)); in dataProcAdrModes()
371 source = amode.value; in dataProcAdrModes()
375 switch (amode.stype) { in dataProcAdrModes()
376 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break; in dataProcAdrModes()
377 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break; in dataProcAdrModes()
378 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break; in dataProcAdrModes()
379 case ROR: mMips->ROTR(tmpReg, amode.reg, amode.value); break; in dataProcAdrModes()
489 if (amode.value > 0xffff) { in dataProcessing()
490 mMips->LUI(Rd, (amode.value >> 16)); in dataProcessing()
491 if (amode.value & 0x0000ffff) { in dataProcessing()
492 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff)); in dataProcessing()
495 mMips->ORI(Rd, 0, amode.value); in dataProcessing()
498 switch (amode.stype) { in dataProcessing()
499 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
500 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; in dataProcessing()
501 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; in dataProcessing()
502 case ROR: mMips->ROTR(Rd, amode.reg, amode.value); break; in dataProcessing()
516 if (amode.value > 0xffff) { in dataProcessing()
517 mMips->LUI(Rd, (amode.value >> 16)); in dataProcessing()
518 if (amode.value & 0x0000ffff) { in dataProcessing()
519 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff)); in dataProcessing()
522 mMips->ORI(Rd, 0, amode.value); in dataProcessing()
525 switch (amode.stype) { in dataProcessing()
526 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
527 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; in dataProcessing()
528 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; in dataProcessing()
529 case ROR: mMips->ROTR(Rd, amode.reg, amode.value); break; in dataProcessing()
757 amode.value = 0; in LDR()
758 amode.writeback = 0; in LDR()
764 mMips->LW(Rd, Rn, amode.value); in LDR()
765 if (amode.writeback) { // OPTIONAL writeback on pre-index mode in LDR()
766 mMips->DADDIU(Rn, Rn, amode.value); in LDR()
774 mMips->DADDIU(Rn, Rn, amode.value); in LDR()
778 mMips->DADDU(R_at, Rn, amode.reg); in LDR()
791 amode.value = 0; in LDRB()
792 amode.writeback = 0; in LDRB()
795 mMips->LBU(Rd, Rn, amode.value); in LDRB()
796 if (amode.writeback) { // OPTIONAL writeback on pre-index mode in LDRB()
797 mMips->DADDIU(Rn, Rn, amode.value); in LDRB()
802 mMips->DADDIU(Rn, Rn, amode.value); in LDRB()
806 mMips->DADDU(R_at, Rn, amode.reg); in LDRB()
820 amode.value = 0; in STR()
821 amode.writeback = 0; in STR()
827 if (amode.writeback) { // OPTIONAL writeback on pre-index mode in STR()
830 mMips->DADDIU(Rn, Rn, amode.value); in STR()
834 mMips->SW(Rd, Rn, amode.value); in STR()
839 mMips->DADDIU(Rn, Rn, amode.value); // post index always writes back in STR()
843 mMips->DADDU(R_at, Rn, amode.reg); in STR()
856 amode.value = 0; in STRB()
857 amode.writeback = 0; in STRB()
860 mMips->SB(Rd, Rn, amode.value); in STRB()
861 if (amode.writeback) { // OPTIONAL writeback on pre-index mode in STRB()
862 mMips->DADDIU(Rn, Rn, amode.value); in STRB()
867 mMips->DADDIU(Rn, Rn, amode.value); in STRB()
871 mMips->DADDU(R_at, Rn, amode.reg); in STRB()
884 amode.value = 0; in LDRH()
887 mMips->LHU(Rd, Rn, amode.value); in LDRH()
891 mMips->DADDIU(Rn, Rn, amode.value); in LDRH()
895 if (amode.reg >= 0) { in LDRH()
896 mMips->DADDU(R_at, Rn, amode.reg); in LDRH()
898 mMips->DSUBU(R_at, Rn, abs(amode.reg)); in LDRH()
928 amode.value = 0; in STRH()
931 mMips->SH(Rd, Rn, amode.value); in STRH()
935 mMips->DADDIU(Rn, Rn, amode.value); in STRH()
939 if (amode.reg >= 0) { in STRH()
940 mMips->DADDU(R_at, Rn, amode.reg); in STRH()
942 mMips->DSUBU(R_at, Rn, abs(amode.reg)); in STRH()
1220 amode.value = 0; in ADDR_LDR()
1221 amode.writeback = 0; in ADDR_LDR()
1227 mMips->LD(Rd, Rn, amode.value); in ADDR_LDR()
1228 if (amode.writeback) { // OPTIONAL writeback on pre-index mode in ADDR_LDR()
1229 mMips->DADDIU(Rn, Rn, amode.value); in ADDR_LDR()
1237 mMips->DADDIU(Rn, Rn, amode.value); in ADDR_LDR()
1241 mMips->DADDU(R_at, Rn, amode.reg); in ADDR_LDR()
1254 amode.value = 0; in ADDR_STR()
1255 amode.writeback = 0; in ADDR_STR()
1261 if (amode.writeback) { // OPTIONAL writeback on pre-index mode in ADDR_STR()
1264 mMips->DADDIU(Rn, Rn, amode.value); in ADDR_STR()
1268 mMips->SD(Rd, Rn, amode.value); in ADDR_STR()
1273 mMips->DADDIU(Rn, Rn, amode.value); // post index always writes back in ADDR_STR()
1277 mMips->DADDU(R_at, Rn, amode.reg); in ADDR_STR()